Lines Matching refs:ah
33 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
39 static void ath9k_hw_set_clockrate(struct ath_hw *ah)
41 struct ath_common *common = ath9k_hw_common(ah);
42 struct ath9k_channel *chan = ah->curchan;
46 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
52 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
69 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
71 struct ath_common *common = ath9k_hw_common(ah);
76 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
83 if ((REG_READ(ah, reg) & mask) == val)
89 ath_dbg(ath9k_hw_common(ah), ANY,
91 timeout, reg, REG_READ(ah, reg), mask, val);
97 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
110 void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,
115 ENABLE_REGWRITE_BUFFER(ah);
117 REG_WRITE(ah, INI_RA(array, r, 0),
121 REGWRITE_BUFFER_FLUSH(ah);
124 void ath9k_hw_read_array(struct ath_hw *ah, u32 array[][2], int size)
131 dev_err(ah->dev, "%s: tmp_reg_list: alloc filed\n", __func__);
137 dev_err(ah->dev, "%s tmp_data: alloc filed\n", __func__);
144 REG_READ_MULTI(ah, tmp_reg_list, tmp_data, size);
166 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
185 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
193 } else if (ah->curchan &&
194 IS_CHAN_HALF_RATE(ah->curchan)) {
211 ath_err(ath9k_hw_common(ah),
221 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
254 static bool ath9k_hw_read_revisions(struct ath_hw *ah)
259 if (ah->get_mac_revision)
260 ah->hw_version.macRev = ah->get_mac_revision();
262 switch (ah->hw_version.devid) {
264 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
267 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
268 if (!ah->get_mac_revision) {
269 val = REG_READ(ah, AR_SREV(ah));
270 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
274 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
277 ah->hw_version.macVersion = AR_SREV_VERSION_9550;
280 ah->hw_version.macVersion = AR_SREV_VERSION_9531;
283 ah->hw_version.macVersion = AR_SREV_VERSION_9561;
287 srev = REG_READ(ah, AR_SREV(ah));
290 ath_err(ath9k_hw_common(ah),
295 val = srev & AR_SREV_ID(ah);
299 ah->hw_version.macVersion =
301 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
303 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
304 ah->is_pciexpress = true;
306 ah->is_pciexpress = (val &
309 if (!AR_SREV_9100(ah))
310 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
312 ah->hw_version.macRev = val & AR_SREV_REVISION;
314 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
315 ah->is_pciexpress = true;
325 static void ath9k_hw_disablepcie(struct ath_hw *ah)
327 if (!AR_SREV_5416(ah))
330 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
331 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
332 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
333 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
334 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
335 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
336 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
337 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
338 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
340 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
344 static bool ath9k_hw_chip_test(struct ath_hw *ah)
346 struct ath_common *common = ath9k_hw_common(ah);
354 if (!AR_SREV_9300_20_OR_LATER(ah)) {
364 regHold[i] = REG_READ(ah, addr);
367 REG_WRITE(ah, addr, wrData);
368 rdData = REG_READ(ah, addr);
378 REG_WRITE(ah, addr, wrData);
379 rdData = REG_READ(ah, addr);
387 REG_WRITE(ah, regAddr[i], regHold[i]);
394 static void ath9k_hw_init_config(struct ath_hw *ah)
396 struct ath_common *common = ath9k_hw_common(ah);
398 ah->config.dma_beacon_response_time = 1;
399 ah->config.sw_beacon_response_time = 6;
400 ah->config.cwm_ignore_extcca = false;
401 ah->config.analog_shiftreg = 1;
403 ah->config.rx_intr_mitigation = true;
405 if (AR_SREV_9300_20_OR_LATER(ah)) {
406 ah->config.rimt_last = 500;
407 ah->config.rimt_first = 2000;
409 ah->config.rimt_last = 250;
410 ah->config.rimt_first = 700;
413 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
414 ah->config.pll_pwrsave = 7;
433 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
435 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
436 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
437 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) &&
438 !ah->is_pciexpress)) {
439 ah->config.serialize_regmode = SER_REG_MODE_ON;
441 ah->config.serialize_regmode = SER_REG_MODE_OFF;
446 ah->config.serialize_regmode);
448 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
449 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
451 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
454 static void ath9k_hw_init_defaults(struct ath_hw *ah)
456 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
461 ah->hw_version.magic = AR5416_MAGIC;
462 ah->hw_version.subvendorid = 0;
464 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE |
466 if (AR_SREV_9100(ah))
467 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
469 ah->slottime = 9;
470 ah->globaltxtimeout = (u32) -1;
471 ah->power_mode = ATH9K_PM_UNDEFINED;
472 ah->htc_reset_init = true;
474 ah->tpc_enabled = false;
476 ah->ani_function = ATH9K_ANI_ALL;
477 if (!AR_SREV_9300_20_OR_LATER(ah))
478 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
480 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
481 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
483 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
486 static void ath9k_hw_init_macaddr(struct ath_hw *ah)
488 struct ath_common *common = ath9k_hw_common(ah);
498 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
516 static int ath9k_hw_post_init(struct ath_hw *ah)
518 struct ath_common *common = ath9k_hw_common(ah);
522 if (!ath9k_hw_chip_test(ah))
526 if (!AR_SREV_9300_20_OR_LATER(ah)) {
527 ecode = ar9002_hw_rf_claim(ah);
532 ecode = ath9k_hw_eeprom_init(ah);
536 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",
537 ah->eep_ops->get_eeprom_ver(ah),
538 ah->eep_ops->get_eeprom_rev(ah));
540 ath9k_hw_ani_init(ah);
546 if (AR_SREV_9300_20_OR_LATER(ah)) {
547 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
549 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ;
550 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ;
557 static int ath9k_hw_attach_ops(struct ath_hw *ah)
559 if (!AR_SREV_9300_20_OR_LATER(ah))
560 return ar9002_hw_attach_ops(ah);
562 ar9003_hw_attach_ops(ah);
567 static int __ath9k_hw_init(struct ath_hw *ah)
569 struct ath_common *common = ath9k_hw_common(ah);
572 if (!ath9k_hw_read_revisions(ah)) {
577 switch (ah->hw_version.macVersion) {
599 ah->hw_version.macVersion, ah->hw_version.macRev);
604 * Read back AR_WA(ah) into a permanent copy and set bits 14 and 17.
608 if (AR_SREV_9300_20_OR_LATER(ah)) {
609 ah->WARegVal = REG_READ(ah, AR_WA(ah));
610 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
614 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
619 if (AR_SREV_9565(ah)) {
620 ah->WARegVal |= AR_WA_BIT22;
621 REG_WRITE(ah, AR_WA(ah), ah->WARegVal);
624 ath9k_hw_init_defaults(ah);
625 ath9k_hw_init_config(ah);
627 r = ath9k_hw_attach_ops(ah);
631 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
636 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
637 AR_SREV_9330(ah) || AR_SREV_9550(ah))
638 ah->is_pciexpress = false;
640 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
641 ath9k_hw_init_cal_settings(ah);
643 if (!ah->is_pciexpress)
644 ath9k_hw_disablepcie(ah);
646 r = ath9k_hw_post_init(ah);
650 ath9k_hw_init_mode_gain_regs(ah);
651 r = ath9k_hw_fill_cap_info(ah);
655 ath9k_hw_init_macaddr(ah);
656 ath9k_hw_init_hang_checks(ah);
663 int ath9k_hw_init(struct ath_hw *ah)
666 struct ath_common *common = ath9k_hw_common(ah);
669 switch (ah->hw_version.devid) {
696 ah->hw_version.devid);
700 ret = __ath9k_hw_init(ah);
708 ath_dynack_init(ah);
714 static void ath9k_hw_init_qos(struct ath_hw *ah)
716 ENABLE_REGWRITE_BUFFER(ah);
718 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
719 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
721 REG_WRITE(ah, AR_QOS_NO_ACK,
726 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
727 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
728 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
729 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
730 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
732 REGWRITE_BUFFER_FLUSH(ah);
735 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
737 struct ath_common *common = ath9k_hw_common(ah);
740 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
742 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
744 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) {
756 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
760 static void ath9k_hw_init_pll(struct ath_hw *ah,
765 pll = ath9k_hw_compute_pll_control(ah, chan);
767 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
769 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
771 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
773 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
776 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
778 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
780 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
783 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
785 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
787 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
791 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
794 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
797 } else if (AR_SREV_9330(ah)) {
800 if (ah->is_clk_25mhz) {
811 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
814 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
817 REG_WRITE(ah, AR_RTC_PLL_CONTROL(ah),
822 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
825 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
826 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
829 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
831 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
832 AR_SREV_9561(ah)) {
835 REG_WRITE(ah, AR_RTC_PLL_CONTROL(ah),
839 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
842 if (ah->is_clk_25mhz) {
843 if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) {
853 if (AR_SREV_9340(ah)) {
859 pll2_divfrac = (AR_SREV_9531(ah) ||
860 AR_SREV_9561(ah)) ?
866 regval = REG_READ(ah, AR_PHY_PLL_MODE);
867 if (AR_SREV_9531(ah) || AR_SREV_9561(ah))
871 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
874 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
878 regval = REG_READ(ah, AR_PHY_PLL_MODE);
879 if (AR_SREV_9340(ah))
885 else if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) {
892 if (AR_SREV_9531(ah))
900 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
902 if (AR_SREV_9531(ah) || AR_SREV_9561(ah))
903 REG_WRITE(ah, AR_PHY_PLL_MODE,
904 REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff);
906 REG_WRITE(ah, AR_PHY_PLL_MODE,
907 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
912 if (AR_SREV_9565(ah))
914 REG_WRITE(ah, AR_RTC_PLL_CONTROL(ah), pll);
916 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
917 AR_SREV_9550(ah))
921 if (AR_SREV_9271(ah)) {
923 REG_WRITE(ah, 0x50040, 0x304);
928 REG_WRITE(ah, AR_RTC_SLEEP_CLK(ah), AR_RTC_FORCE_DERIVED_CLK);
931 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
942 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
943 AR_SREV_9561(ah))
946 if (AR_SREV_9300_20_OR_LATER(ah)) {
948 if (ah->config.rx_intr_mitigation) {
956 if (ah->config.rx_intr_mitigation) {
965 if (ah->config.tx_intr_mitigation) {
973 ENABLE_REGWRITE_BUFFER(ah);
975 REG_WRITE(ah, AR_IMR, imr_reg);
976 ah->imrs2_reg |= AR_IMR_S2_GTT;
977 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
979 if (ah->msi_enabled) {
980 ah->msi_reg = REG_READ(ah, AR_PCIE_MSI(ah));
981 ah->msi_reg |= AR_PCIE_MSI_HW_DBI_WR_EN;
982 ah->msi_reg &= AR_PCIE_MSI_HW_INT_PENDING_ADDR_MSI_64;
983 REG_WRITE(ah, AR_INTCFG, msi_cfg);
984 ath_dbg(ath9k_hw_common(ah), ANY,
986 REG_READ(ah, AR_INTCFG), msi_cfg);
989 if (!AR_SREV_9100(ah)) {
990 REG_WRITE(ah, AR_INTR_SYNC_CAUSE(ah), 0xFFFFFFFF);
991 REG_WRITE(ah, AR_INTR_SYNC_ENABLE(ah), sync_default);
992 REG_WRITE(ah, AR_INTR_SYNC_MASK(ah), 0);
995 REGWRITE_BUFFER_FLUSH(ah);
997 if (AR_SREV_9300_20_OR_LATER(ah)) {
998 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE(ah), 0);
999 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK(ah), 0);
1000 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE(ah), 0);
1001 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK(ah), 0);
1005 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
1007 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
1009 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
1012 void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
1014 u32 val = ath9k_hw_mac_to_clks(ah, us);
1016 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
1019 void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1021 u32 val = ath9k_hw_mac_to_clks(ah, us);
1023 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
1026 void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1028 u32 val = ath9k_hw_mac_to_clks(ah, us);
1030 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
1033 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1036 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n",
1038 ah->globaltxtimeout = (u32) -1;
1041 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1042 ah->globaltxtimeout = tu;
1047 void ath9k_hw_init_global_settings(struct ath_hw *ah)
1049 struct ath_common *common = ath9k_hw_common(ah);
1050 const struct ath9k_channel *chan = ah->curchan;
1057 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",
1058 ah->misc_mode);
1063 if (ah->misc_mode != 0)
1064 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
1066 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1081 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1092 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1100 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1104 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1106 reg = REG_READ(ah, AR_USEC);
1111 slottime = ah->slottime;
1115 slottime += 3 * ah->coverage_class;
1128 acktimeout += 64 - sifstime - ah->slottime;
1129 ctstimeout += 48 - sifstime - ah->slottime;
1132 if (ah->dynack.enabled) {
1133 acktimeout = ah->dynack.ackto;
1137 ah->dynack.ackto = acktimeout;
1140 ath9k_hw_set_sifs_time(ah, sifstime);
1141 ath9k_hw_setslottime(ah, slottime);
1142 ath9k_hw_set_ack_timeout(ah, acktimeout);
1143 ath9k_hw_set_cts_timeout(ah, ctstimeout);
1144 if (ah->globaltxtimeout != (u32) -1)
1145 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1147 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1148 REG_RMW(ah, AR_USEC,
1155 REG_RMW(ah, AR_TXSIFS,
1161 void ath9k_hw_deinit(struct ath_hw *ah)
1163 struct ath_common *common = ath9k_hw_common(ah);
1168 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1192 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1194 struct ath_common *common = ath9k_hw_common(ah);
1197 ENABLE_REGWRITE_BUFFER(ah);
1202 if (!AR_SREV_9300_20_OR_LATER(ah))
1203 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
1208 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
1210 REGWRITE_BUFFER_FLUSH(ah);
1217 if (!AR_SREV_9300_20_OR_LATER(ah))
1218 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1220 ENABLE_REGWRITE_BUFFER(ah);
1225 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
1230 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1232 if (AR_SREV_9300_20_OR_LATER(ah)) {
1233 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1234 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1236 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1237 ah->caps.rx_status_len);
1244 if (AR_SREV_9285(ah)) {
1250 } else if (AR_SREV_9340_13_OR_LATER(ah)) {
1257 if (!AR_SREV_9271(ah))
1258 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size);
1260 REGWRITE_BUFFER_FLUSH(ah);
1262 if (AR_SREV_9300_20_OR_LATER(ah))
1263 ath9k_hw_reset_txstatus_ring(ah);
1266 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1271 ENABLE_REG_RMW_BUFFER(ah);
1274 if (!AR_SREV_9340_13(ah)) {
1276 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1286 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1289 if (!ah->is_monitoring)
1293 REG_RMW(ah, AR_STA_ID1, set, mask);
1294 REG_RMW_BUFFER_FLUSH(ah);
1297 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1319 static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type)
1324 npend = ath9k_hw_numtxpending(ah, i);
1329 if (ah->external_reset &&
1333 ath_dbg(ath9k_hw_common(ah), RESET,
1336 reset_err = ah->external_reset();
1338 ath_err(ath9k_hw_common(ah),
1344 REG_WRITE(ah, AR_RTC_RESET(ah), 1);
1350 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1355 if (AR_SREV_9100(ah)) {
1356 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK(ah),
1358 (void)REG_READ(ah, AR_RTC_DERIVED_CLK(ah));
1361 ENABLE_REGWRITE_BUFFER(ah);
1363 if (AR_SREV_9300_20_OR_LATER(ah)) {
1364 REG_WRITE(ah, AR_WA(ah), ah->WARegVal);
1368 REG_WRITE(ah, AR_RTC_FORCE_WAKE(ah), AR_RTC_FORCE_WAKE_EN |
1371 if (AR_SREV_9100(ah)) {
1375 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE(ah));
1376 if (AR_SREV_9340(ah))
1384 REG_WRITE(ah, AR_INTR_SYNC_ENABLE(ah), 0);
1387 if (!AR_SREV_9300_20_OR_LATER(ah))
1389 REG_WRITE(ah, AR_RC, val);
1391 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1392 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1399 if (AR_SREV_9330(ah)) {
1400 if (!ath9k_hw_ar9330_reset_war(ah, type))
1404 if (ath9k_hw_mci_is_enabled(ah))
1405 ar9003_mci_check_gpm_offset(ah);
1410 if (AR_SREV_9300(ah) || AR_SREV_9580(ah)) {
1411 REG_SET_BIT(ah, AR_CFG, AR_CFG_HALT_REQ);
1412 ath9k_hw_wait(ah, AR_CFG, AR_CFG_HALT_ACK, AR_CFG_HALT_ACK,
1414 REG_CLR_BIT(ah, AR_CFG, AR_CFG_HALT_REQ);
1417 REG_WRITE(ah, AR_RTC_RC(ah), rst_flags);
1419 REGWRITE_BUFFER_FLUSH(ah);
1421 if (AR_SREV_9300_20_OR_LATER(ah))
1423 else if (AR_SREV_9100(ah))
1428 REG_WRITE(ah, AR_RTC_RC(ah), 0);
1429 if (!ath9k_hw_wait(ah, AR_RTC_RC(ah), AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1430 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");
1434 if (!AR_SREV_9100(ah))
1435 REG_WRITE(ah, AR_RC, 0);
1437 if (AR_SREV_9100(ah))
1443 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1445 ENABLE_REGWRITE_BUFFER(ah);
1447 if (AR_SREV_9300_20_OR_LATER(ah)) {
1448 REG_WRITE(ah, AR_WA(ah), ah->WARegVal);
1452 REG_WRITE(ah, AR_RTC_FORCE_WAKE(ah), AR_RTC_FORCE_WAKE_EN |
1455 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1456 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1458 REG_WRITE(ah, AR_RTC_RESET(ah), 0);
1460 REGWRITE_BUFFER_FLUSH(ah);
1464 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1465 REG_WRITE(ah, AR_RC, 0);
1467 REG_WRITE(ah, AR_RTC_RESET(ah), 1);
1469 if (!ath9k_hw_wait(ah,
1470 AR_RTC_STATUS(ah),
1471 AR_RTC_STATUS_M(ah),
1474 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");
1478 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1481 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1485 if (AR_SREV_9300_20_OR_LATER(ah)) {
1486 REG_WRITE(ah, AR_WA(ah), ah->WARegVal);
1490 REG_WRITE(ah, AR_RTC_FORCE_WAKE(ah),
1493 if (!ah->reset_power_on)
1498 ret = ath9k_hw_set_reset_power_on(ah);
1500 ah->reset_power_on = true;
1504 ret = ath9k_hw_set_reset(ah, type);
1513 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1518 if (AR_SREV_9280(ah)) {
1519 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1523 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) ||
1524 (REG_READ(ah, AR_CR) & AR_CR_RXE(ah)))
1527 if (!ath9k_hw_set_reset_reg(ah, reset_type))
1530 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1533 ah->chip_fullsleep = false;
1535 if (AR_SREV_9330(ah))
1536 ar9003_hw_internal_regulator_apply(ah);
1537 ath9k_hw_init_pll(ah, chan);
1542 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1545 struct ath_common *common = ath9k_hw_common(ah);
1546 struct ath9k_hw_capabilities *pCap = &ah->caps;
1553 u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags;
1559 if (ath9k_hw_numtxpending(ah, qnum)) {
1566 if (!ath9k_hw_rfbus_req(ah)) {
1572 ath9k_hw_mark_phy_inactive(ah);
1576 ath9k_hw_init_pll(ah, chan);
1578 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1584 ath9k_hw_set_channel_regs(ah, chan);
1586 r = ath9k_hw_rf_set_freq(ah, chan);
1591 ath9k_hw_set_clockrate(ah);
1592 ath9k_hw_apply_txpower(ah, chan, false);
1594 ath9k_hw_set_delta_slope(ah, chan);
1595 ath9k_hw_spur_mitigate_freq(ah, chan);
1598 ah->eep_ops->set_board_values(ah, chan);
1600 ath9k_hw_init_bb(ah, chan);
1601 ath9k_hw_rfbus_done(ah);
1604 ah->ah_flags |= AH_FASTCC;
1605 ath9k_hw_init_cal(ah, chan);
1606 ah->ah_flags &= ~AH_FASTCC;
1612 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1614 u32 gpio_mask = ah->gpio_mask;
1621 ath9k_hw_gpio_request_out(ah, i, NULL,
1623 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1627 void ath9k_hw_check_nav(struct ath_hw *ah)
1629 struct ath_common *common = ath9k_hw_common(ah);
1632 val = REG_READ(ah, AR_NAV);
1635 REG_WRITE(ah, AR_NAV, 0);
1640 bool ath9k_hw_check_alive(struct ath_hw *ah)
1646 if (REG_READ(ah, AR_CFG) == 0xdeadbeef)
1649 if (AR_SREV_9300(ah))
1650 return !ath9k_hw_detect_mac_hang(ah);
1652 if (AR_SREV_9285_12_OR_LATER(ah))
1655 last_val = REG_READ(ah, AR_OBS_BUS_1);
1657 reg = REG_READ(ah, AR_OBS_BUS_1);
1680 static void ath9k_hw_init_mfp(struct ath_hw *ah)
1683 if (AR_SREV_9280_20_OR_LATER(ah)) {
1686 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1688 if (AR_SREV_9271(ah) || AR_DEVID_7010(ah))
1689 ah->sw_mgmt_crypto_tx = true;
1691 ah->sw_mgmt_crypto_tx = false;
1692 ah->sw_mgmt_crypto_rx = false;
1693 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1695 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1697 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1699 ah->sw_mgmt_crypto_tx = true;
1700 ah->sw_mgmt_crypto_rx = true;
1702 ah->sw_mgmt_crypto_tx = true;
1703 ah->sw_mgmt_crypto_rx = true;
1707 static void ath9k_hw_reset_opmode(struct ath_hw *ah,
1710 struct ath_common *common = ath9k_hw_common(ah);
1712 ENABLE_REGWRITE_BUFFER(ah);
1714 REG_RMW(ah, AR_STA_ID1, macStaId1
1716 | ah->sta_id1_defaults,
1719 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1720 ath9k_hw_write_associd(ah);
1721 REG_WRITE(ah, AR_ISR, ~0);
1722 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1724 REGWRITE_BUFFER_FLUSH(ah);
1726 ath9k_hw_set_operating_mode(ah, ah->opmode);
1729 static void ath9k_hw_init_queues(struct ath_hw *ah)
1733 ENABLE_REGWRITE_BUFFER(ah);
1736 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1738 REGWRITE_BUFFER_FLUSH(ah);
1740 ah->intr_txqs = 0;
1742 ath9k_hw_resettxqueue(ah, i);
1748 static void ath9k_hw_init_desc(struct ath_hw *ah)
1750 struct ath_common *common = ath9k_hw_common(ah);
1752 if (AR_SREV_9100(ah)) {
1754 mask = REG_READ(ah, AR_CFG);
1760 REG_WRITE(ah, AR_CFG, mask);
1762 REG_READ(ah, AR_CFG));
1767 if (AR_SREV_9271(ah))
1768 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1770 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1773 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) ||
1774 AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
1775 AR_SREV_9561(ah))
1776 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1778 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1787 static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
1789 struct ath_common *common = ath9k_hw_common(ah);
1790 struct ath9k_hw_capabilities *pCap = &ah->caps;
1793 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1796 if (ah->chip_fullsleep)
1799 if (!ah->curchan)
1802 if (chan->channel == ah->curchan->channel)
1805 if ((ah->curchan->channelFlags | chan->channelFlags) &
1813 ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT))
1816 if (!ath9k_hw_check_alive(ah))
1823 if (AR_SREV_9462(ah) && (ah->caldata &&
1824 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) ||
1825 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) ||
1826 !test_bit(RTT_DONE, &ah->caldata->cal_flags))))
1830 ah->curchan->channel, chan->channel);
1832 ret = ath9k_hw_channel_change(ah, chan);
1836 if (ath9k_hw_mci_is_enabled(ah))
1837 ar9003_mci_2g5g_switch(ah, false);
1839 ath9k_hw_loadnf(ah, ah->curchan);
1840 ath9k_hw_start_nfcal(ah, true);
1842 if (AR_SREV_9271(ah))
1843 ar9002_hw_load_ani_reg(ah, chan);
1867 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1870 struct ath_common *common = ath9k_hw_common(ah);
1879 bool save_fullsleep = ah->chip_fullsleep;
1881 if (ath9k_hw_mci_is_enabled(ah)) {
1882 start_mci_reset = ar9003_mci_start_reset(ah, chan);
1887 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1890 if (ah->curchan && !ah->chip_fullsleep)
1891 ath9k_hw_getnf(ah, ah->curchan);
1893 ah->caldata = caldata;
1898 ath9k_init_nfcal_hist_buffer(ah, chan);
1902 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor);
1905 r = ath9k_hw_do_fastcc(ah, chan);
1910 if (ath9k_hw_mci_is_enabled(ah))
1911 ar9003_mci_stop_bt(ah, save_fullsleep);
1913 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1917 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1921 tsf = ath9k_hw_gettsf64(ah);
1923 saveLedState = REG_READ(ah, AR_CFG_LED) &
1927 ath9k_hw_mark_phy_inactive(ah);
1929 ah->paprd_table_write_done = false;
1932 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1933 REG_WRITE(ah,
1939 if (!ath9k_hw_chip_reset(ah, chan)) {
1945 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1946 ah->htc_reset_init = false;
1947 REG_WRITE(ah,
1955 ath9k_hw_settsf64(ah, tsf + tsf_offset);
1957 if (AR_SREV_9280_20_OR_LATER(ah))
1958 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL(ah), AR_GPIO_JTAG_DISABLE);
1960 if (!AR_SREV_9300_20_OR_LATER(ah))
1961 ar9002_hw_enable_async_fifo(ah);
1963 r = ath9k_hw_process_ini(ah, chan);
1967 ath9k_hw_set_rfmode(ah, chan);
1969 if (ath9k_hw_mci_is_enabled(ah))
1970 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1977 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1979 ath9k_hw_settsf64(ah, tsf + tsf_offset);
1982 ath9k_hw_init_mfp(ah);
1984 ath9k_hw_set_delta_slope(ah, chan);
1985 ath9k_hw_spur_mitigate_freq(ah, chan);
1986 ah->eep_ops->set_board_values(ah, chan);
1988 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna);
1990 r = ath9k_hw_rf_set_freq(ah, chan);
1994 ath9k_hw_set_clockrate(ah);
1996 ath9k_hw_init_queues(ah);
1997 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1998 ath9k_hw_ani_cache_ini_regs(ah);
1999 ath9k_hw_init_qos(ah);
2001 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2002 ath9k_hw_gpio_request_in(ah, ah->rfkill_gpio, "ath9k-rfkill");
2004 ath9k_hw_init_global_settings(ah);
2006 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
2007 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2009 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2011 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2015 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
2017 ath9k_hw_set_dma(ah);
2019 if (!ath9k_hw_mci_is_enabled(ah))
2020 REG_WRITE(ah, AR_OBS(ah), 8);
2022 ENABLE_REG_RMW_BUFFER(ah);
2023 if (ah->config.rx_intr_mitigation) {
2024 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, ah->config.rimt_last);
2025 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, ah->config.rimt_first);
2028 if (ah->config.tx_intr_mitigation) {
2029 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
2030 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
2032 REG_RMW_BUFFER_FLUSH(ah);
2034 ath9k_hw_init_bb(ah, chan);
2040 if (!ath9k_hw_init_cal(ah, chan))
2043 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata))
2046 ENABLE_REGWRITE_BUFFER(ah);
2048 ath9k_hw_restore_chainmask(ah);
2049 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2051 REGWRITE_BUFFER_FLUSH(ah);
2053 ath9k_hw_gen_timer_start_tsf2(ah);
2055 ath9k_hw_init_desc(ah);
2057 if (ath9k_hw_btcoex_is_enabled(ah))
2058 ath9k_hw_btcoex_enable(ah);
2060 if (ath9k_hw_mci_is_enabled(ah))
2061 ar9003_mci_check_bt(ah);
2063 if (AR_SREV_9300_20_OR_LATER(ah)) {
2064 ath9k_hw_loadnf(ah, chan);
2065 ath9k_hw_start_nfcal(ah, true);
2068 if (AR_SREV_9300_20_OR_LATER(ah))
2069 ar9003_hw_bb_watchdog_config(ah);
2071 if (ah->config.hw_hang_checks & HW_PHYRESTART_CLC_WAR)
2072 ar9003_hw_disable_phy_restart(ah);
2074 ath9k_hw_apply_gpio_override(ah);
2076 if (AR_SREV_9565(ah) && common->bt_ant_diversity)
2077 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON);
2079 if (ah->hw->conf.radar_enabled) {
2081 ah->radar_conf.ext_channel = IS_CHAN_HT40(chan);
2082 ath9k_hw_set_radar_params(ah);
2097 static void ath9k_set_power_sleep(struct ath_hw *ah)
2099 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2101 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2102 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff);
2103 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff);
2104 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff);
2106 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
2114 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE(ah), AR_RTC_FORCE_WAKE_EN);
2116 if (ath9k_hw_mci_is_enabled(ah))
2119 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
2120 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2123 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
2124 REG_CLR_BIT(ah, AR_RTC_RESET(ah), AR_RTC_RESET_EN);
2128 /* Clear Bit 14 of AR_WA(ah) after putting chip into Full Sleep mode. */
2129 if (AR_SREV_9300_20_OR_LATER(ah))
2130 REG_WRITE(ah, AR_WA(ah), ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
2138 static void ath9k_set_power_network_sleep(struct ath_hw *ah)
2140 struct ath9k_hw_capabilities *pCap = &ah->caps;
2142 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2146 REG_WRITE(ah, AR_RTC_FORCE_WAKE(ah),
2159 if (ath9k_hw_mci_is_enabled(ah))
2160 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
2166 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE(ah), AR_RTC_FORCE_WAKE_EN);
2168 if (ath9k_hw_mci_is_enabled(ah))
2172 /* Clear Bit 14 of AR_WA(ah) after putting chip into Net Sleep mode. */
2173 if (AR_SREV_9300_20_OR_LATER(ah))
2174 REG_WRITE(ah, AR_WA(ah), ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
2177 static bool ath9k_hw_set_power_awake(struct ath_hw *ah)
2182 /* Set Bits 14 and 17 of AR_WA(ah) before powering on the chip. */
2183 if (AR_SREV_9300_20_OR_LATER(ah)) {
2184 REG_WRITE(ah, AR_WA(ah), ah->WARegVal);
2188 if ((REG_READ(ah, AR_RTC_STATUS(ah)) &
2189 AR_RTC_STATUS_M(ah)) == AR_RTC_STATUS_SHUTDOWN) {
2190 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
2193 if (!AR_SREV_9300_20_OR_LATER(ah))
2194 ath9k_hw_init_pll(ah, NULL);
2196 if (AR_SREV_9100(ah))
2197 REG_SET_BIT(ah, AR_RTC_RESET(ah),
2200 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE(ah),
2202 if (AR_SREV_9100(ah))
2208 val = REG_READ(ah, AR_RTC_STATUS(ah)) & AR_RTC_STATUS_M(ah);
2212 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE(ah),
2216 ath_err(ath9k_hw_common(ah),
2222 if (ath9k_hw_mci_is_enabled(ah))
2223 ar9003_mci_set_power_awake(ah);
2225 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2230 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2232 struct ath_common *common = ath9k_hw_common(ah);
2241 if (ah->power_mode == mode)
2245 modes[ah->power_mode], modes[mode]);
2249 status = ath9k_hw_set_power_awake(ah);
2252 if (ath9k_hw_mci_is_enabled(ah))
2253 ar9003_mci_set_full_sleep(ah);
2255 ath9k_set_power_sleep(ah);
2256 ah->chip_fullsleep = true;
2259 ath9k_set_power_network_sleep(ah);
2265 ah->power_mode = mode;
2273 if (!(ah->ah_flags & AH_UNPLUGGED))
2284 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2288 ENABLE_REGWRITE_BUFFER(ah);
2290 switch (ah->opmode) {
2292 REG_SET_BIT(ah, AR_TXCFG,
2297 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2298 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2299 TU_TO_USEC(ah->config.dma_beacon_response_time));
2300 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2301 TU_TO_USEC(ah->config.sw_beacon_response_time));
2306 ath_dbg(ath9k_hw_common(ah), BEACON,
2307 "%s: unsupported opmode: %d\n", __func__, ah->opmode);
2311 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2312 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2313 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
2315 REGWRITE_BUFFER_FLUSH(ah);
2317 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2321 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
2325 struct ath9k_hw_capabilities *pCap = &ah->caps;
2326 struct ath_common *common = ath9k_hw_common(ah);
2328 ENABLE_REGWRITE_BUFFER(ah);
2330 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt);
2331 REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval);
2332 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval);
2334 REGWRITE_BUFFER_FLUSH(ah);
2336 REG_RMW_FIELD(ah, AR_RSSI_THR,
2358 ENABLE_REGWRITE_BUFFER(ah);
2360 REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP);
2361 REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP);
2363 REG_WRITE(ah, AR_SLEEP1,
2372 REG_WRITE(ah, AR_SLEEP2,
2375 REG_WRITE(ah, AR_TIM_PERIOD, beaconintval);
2376 REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod);
2378 REGWRITE_BUFFER_FLUSH(ah);
2380 REG_SET_BIT(ah, AR_TIMER_MODE,
2385 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
2404 * @ah: the atheros hardware data structure
2415 static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
2418 switch (ah->hw_version.macVersion) {
2429 static void ath9k_gpio_cap_init(struct ath_hw *ah)
2431 struct ath9k_hw_capabilities *pCap = &ah->caps;
2433 if (AR_SREV_9271(ah)) {
2436 } else if (AR_DEVID_7010(ah)) {
2439 } else if (AR_SREV_9287(ah)) {
2442 } else if (AR_SREV_9285(ah)) {
2445 } else if (AR_SREV_9280(ah)) {
2448 } else if (AR_SREV_9300(ah)) {
2451 } else if (AR_SREV_9330(ah)) {
2454 } else if (AR_SREV_9340(ah)) {
2457 } else if (AR_SREV_9462(ah)) {
2460 } else if (AR_SREV_9485(ah)) {
2463 } else if (AR_SREV_9531(ah)) {
2466 } else if (AR_SREV_9550(ah)) {
2469 } else if (AR_SREV_9561(ah)) {
2472 } else if (AR_SREV_9565(ah)) {
2475 } else if (AR_SREV_9580(ah)) {
2484 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2486 struct ath9k_hw_capabilities *pCap = &ah->caps;
2487 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2488 struct ath_common *common = ath9k_hw_common(ah);
2493 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2496 if (ah->opmode != NL80211_IFTYPE_AP &&
2497 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2507 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
2510 if (ah->disable_5ghz)
2517 if (ah->disable_2ghz)
2528 ath9k_gpio_cap_init(ah);
2530 if (AR_SREV_9485(ah) ||
2531 AR_SREV_9285(ah) ||
2532 AR_SREV_9330(ah) ||
2533 AR_SREV_9565(ah))
2535 else if (!AR_SREV_9280_20_OR_LATER(ah))
2537 else if (!AR_SREV_9300_20_OR_LATER(ah) ||
2538 AR_SREV_9340(ah) ||
2539 AR_SREV_9462(ah) ||
2540 AR_SREV_9531(ah))
2545 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2550 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2552 !(AR_SREV_9271(ah)))
2554 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2555 else if (AR_SREV_9100(ah))
2559 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2563 ah->txchainmask = pCap->tx_chainmask;
2564 ah->rxchainmask = pCap->rx_chainmask;
2566 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2569 if (AR_SREV_9300_20_OR_LATER(ah))
2570 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2574 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
2579 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
2585 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2586 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2587 ah->rfkill_gpio =
2588 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2589 ah->rfkill_polarity =
2590 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2595 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
2600 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2605 if (AR_SREV_9300_20_OR_LATER(ah)) {
2607 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) &&
2608 !AR_SREV_9561(ah) && !AR_SREV_9565(ah))
2618 if (AR_SREV_9280_20(ah))
2622 if (AR_SREV_9300_20_OR_LATER(ah))
2625 if (AR_SREV_9561(ah))
2626 ah->ent_mode = 0x3BDA000;
2627 else if (AR_SREV_9300_20_OR_LATER(ah))
2628 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2630 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
2633 if (AR_SREV_9285(ah)) {
2634 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2636 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2644 if (AR_SREV_9300_20_OR_LATER(ah)) {
2645 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2649 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
2650 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2657 if (ath9k_hw_dfs_tested(ah))
2672 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2673 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
2676 if (AR_SREV_9462_20_OR_LATER(ah))
2680 if (AR_SREV_9300_20_OR_LATER(ah) &&
2681 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2685 if (AR_SREV_9462_20_OR_LATER(ah) || AR_SREV_9565_11_OR_LATER(ah))
2686 ah->wow.max_patterns = MAX_NUM_PATTERN;
2688 ah->wow.max_patterns = MAX_NUM_PATTERN_LEGACY;
2698 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, u32 gpio, u32 type)
2704 addr = AR_GPIO_OUTPUT_MUX3(ah);
2706 addr = AR_GPIO_OUTPUT_MUX2(ah);
2708 addr = AR_GPIO_OUTPUT_MUX1(ah);
2712 if (AR_SREV_9280_20_OR_LATER(ah) ||
2713 (addr != AR_GPIO_OUTPUT_MUX1(ah))) {
2714 REG_RMW(ah, addr, (type << gpio_shift),
2717 tmp = REG_READ(ah, addr);
2721 REG_WRITE(ah, addr, tmp);
2727 static void ath9k_hw_gpio_cfg_soc(struct ath_hw *ah, u32 gpio, bool out,
2732 if (ah->caps.gpio_requested & BIT(gpio))
2737 ath_err(ath9k_hw_common(ah), "request GPIO%d failed:%d\n",
2742 ah->caps.gpio_requested |= BIT(gpio);
2745 static void ath9k_hw_gpio_cfg_wmac(struct ath_hw *ah, u32 gpio, bool out,
2750 if (AR_DEVID_7010(ah)) {
2753 REG_RMW(ah, AR7010_GPIO_OE, gpio_set << gpio_shift,
2755 } else if (AR_SREV_SOC(ah)) {
2757 REG_RMW(ah, AR_GPIO_OE_OUT(ah), gpio_set << gpio_shift,
2763 REG_RMW(ah, AR_GPIO_OE_OUT(ah), gpio_set << gpio_shift,
2767 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2771 static void ath9k_hw_gpio_request(struct ath_hw *ah, u32 gpio, bool out,
2774 WARN_ON(gpio >= ah->caps.num_gpio_pins);
2776 if (BIT(gpio) & ah->caps.gpio_mask)
2777 ath9k_hw_gpio_cfg_wmac(ah, gpio, out, ah_signal_type);
2778 else if (AR_SREV_SOC(ah))
2779 ath9k_hw_gpio_cfg_soc(ah, gpio, out, label);
2784 void ath9k_hw_gpio_request_in(struct ath_hw *ah, u32 gpio, const char *label)
2786 ath9k_hw_gpio_request(ah, gpio, false, label, 0);
2790 void ath9k_hw_gpio_request_out(struct ath_hw *ah, u32 gpio, const char *label,
2793 ath9k_hw_gpio_request(ah, gpio, true, label, ah_signal_type);
2797 void ath9k_hw_gpio_free(struct ath_hw *ah, u32 gpio)
2799 if (!AR_SREV_SOC(ah))
2802 WARN_ON(gpio >= ah->caps.num_gpio_pins);
2804 if (ah->caps.gpio_requested & BIT(gpio)) {
2806 ah->caps.gpio_requested &= ~BIT(gpio);
2811 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2816 (MS(REG_READ(ah, AR_GPIO_IN_OUT(ah)), x##_GPIO_IN_VAL) & BIT(y))
2818 WARN_ON(gpio >= ah->caps.num_gpio_pins);
2820 if (BIT(gpio) & ah->caps.gpio_mask) {
2821 if (AR_SREV_9271(ah))
2823 else if (AR_SREV_9287(ah))
2825 else if (AR_SREV_9285(ah))
2827 else if (AR_SREV_9280(ah))
2829 else if (AR_DEVID_7010(ah))
2830 val = REG_READ(ah, AR7010_GPIO_IN) & BIT(gpio);
2831 else if (AR_SREV_9300_20_OR_LATER(ah))
2832 val = REG_READ(ah, AR_GPIO_IN(ah)) & BIT(gpio);
2835 } else if (BIT(gpio) & ah->caps.gpio_requested) {
2845 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2847 WARN_ON(gpio >= ah->caps.num_gpio_pins);
2849 if (AR_DEVID_7010(ah) || AR_SREV_9271(ah))
2854 if (BIT(gpio) & ah->caps.gpio_mask) {
2855 u32 out_addr = AR_DEVID_7010(ah) ?
2856 AR7010_GPIO_OUT : AR_GPIO_IN_OUT(ah);
2858 REG_RMW(ah, out_addr, val << gpio, BIT(gpio));
2859 } else if (BIT(gpio) & ah->caps.gpio_requested) {
2867 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2869 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2877 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2879 u32 bits = REG_READ(ah, AR_RX_FILTER);
2880 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2891 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2895 ENABLE_REGWRITE_BUFFER(ah);
2897 REG_WRITE(ah, AR_RX_FILTER, bits);
2904 REG_WRITE(ah, AR_PHY_ERR, phybits);
2907 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2909 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2911 REGWRITE_BUFFER_FLUSH(ah);
2915 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2917 if (ath9k_hw_mci_is_enabled(ah))
2918 ar9003_mci_bt_gain_ctrl(ah);
2920 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2923 ath9k_hw_init_pll(ah, NULL);
2924 ah->htc_reset_init = true;
2929 bool ath9k_hw_disable(struct ath_hw *ah)
2931 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2934 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2937 ath9k_hw_init_pll(ah, NULL);
2942 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
2951 return ah->eep_ops->get_eeprom(ah, gain_param);
2954 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
2957 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2972 ah->eep_ops->set_txpower(ah, chan, ctl,
2973 get_antenna_gain(ah, chan), new_pwr, test);
2976 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2978 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2979 struct ath9k_channel *chan = ah->curchan;
2986 ath9k_hw_apply_txpower(ah, chan, test);
2993 void ath9k_hw_setopmode(struct ath_hw *ah)
2995 ath9k_hw_set_operating_mode(ah, ah->opmode);
2999 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3001 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3002 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3006 void ath9k_hw_write_associd(struct ath_hw *ah)
3008 struct ath_common *common = ath9k_hw_common(ah);
3010 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
3011 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
3018 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3023 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
3025 tsf_lower = REG_READ(ah, AR_TSF_L32);
3026 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
3038 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3040 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3041 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3045 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3047 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
3049 ath_dbg(ath9k_hw_common(ah), RESET,
3052 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3056 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set)
3059 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3061 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3065 void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan)
3069 if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca)
3074 REG_WRITE(ah, AR_2040_MODE, macmode);
3108 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
3110 return REG_READ(ah, AR_TSF_L32);
3114 void ath9k_hw_gen_timer_start_tsf2(struct ath_hw *ah)
3116 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3119 REG_SET_BIT(ah, AR_DIRECT_CONNECT, AR_DC_AP_STA_EN);
3120 REG_SET_BIT(ah, AR_RESET_TSF, AR_RESET_TSF2_ONCE);
3124 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
3130 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3138 !AR_SREV_9300_20_OR_LATER(ah))
3154 ath9k_hw_gen_timer_start_tsf2(ah);
3161 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3166 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3174 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3176 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3178 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3181 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3188 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3191 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3202 REG_SET_BIT(ah, AR_IMR_S5, mask);
3204 if ((ah->imask & ATH9K_INT_GENTIMER) == 0) {
3205 ah->imask |= ATH9K_INT_GENTIMER;
3206 ath9k_hw_set_interrupts(ah);
3211 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
3213 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3216 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3219 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3224 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3230 REG_CLR_BIT(ah, AR_IMR_S5,
3237 ah->imask &= ~ATH9K_INT_GENTIMER;
3238 ath9k_hw_set_interrupts(ah);
3243 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3245 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3256 void ath_gen_timer_isr(struct ath_hw *ah)
3258 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3264 trigger_mask = ah->intr_gen_timer_trigger;
3265 thresh_mask = ah->intr_gen_timer_thresh;
3365 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3370 if (AR_SREV_9280_20_OR_LATER(ah)) {
3373 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3374 ah->hw_version.macRev);
3379 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3380 ah->hw_version.macRev,
3381 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev
3383 ah->hw_version.phyRev);