Lines Matching defs:pCap
1546 struct ath9k_hw_capabilities *pCap = &ah->caps;
1552 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) {
1790 struct ath9k_hw_capabilities *pCap = &ah->caps;
1812 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) &&
2140 struct ath9k_hw_capabilities *pCap = &ah->caps;
2144 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2325 struct ath9k_hw_capabilities *pCap = &ah->caps;
2367 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2431 struct ath9k_hw_capabilities *pCap = &ah->caps;
2434 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2435 pCap->gpio_mask = AR9271_GPIO_MASK;
2437 pCap->num_gpio_pins = AR7010_NUM_GPIO;
2438 pCap->gpio_mask = AR7010_GPIO_MASK;
2440 pCap->num_gpio_pins = AR9287_NUM_GPIO;
2441 pCap->gpio_mask = AR9287_GPIO_MASK;
2443 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2444 pCap->gpio_mask = AR9285_GPIO_MASK;
2446 pCap->num_gpio_pins = AR9280_NUM_GPIO;
2447 pCap->gpio_mask = AR9280_GPIO_MASK;
2449 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2450 pCap->gpio_mask = AR9300_GPIO_MASK;
2452 pCap->num_gpio_pins = AR9330_NUM_GPIO;
2453 pCap->gpio_mask = AR9330_GPIO_MASK;
2455 pCap->num_gpio_pins = AR9340_NUM_GPIO;
2456 pCap->gpio_mask = AR9340_GPIO_MASK;
2458 pCap->num_gpio_pins = AR9462_NUM_GPIO;
2459 pCap->gpio_mask = AR9462_GPIO_MASK;
2461 pCap->num_gpio_pins = AR9485_NUM_GPIO;
2462 pCap->gpio_mask = AR9485_GPIO_MASK;
2464 pCap->num_gpio_pins = AR9531_NUM_GPIO;
2465 pCap->gpio_mask = AR9531_GPIO_MASK;
2467 pCap->num_gpio_pins = AR9550_NUM_GPIO;
2468 pCap->gpio_mask = AR9550_GPIO_MASK;
2470 pCap->num_gpio_pins = AR9561_NUM_GPIO;
2471 pCap->gpio_mask = AR9561_GPIO_MASK;
2473 pCap->num_gpio_pins = AR9565_NUM_GPIO;
2474 pCap->gpio_mask = AR9565_GPIO_MASK;
2476 pCap->num_gpio_pins = AR9580_NUM_GPIO;
2477 pCap->gpio_mask = AR9580_GPIO_MASK;
2479 pCap->num_gpio_pins = AR_NUM_GPIO;
2480 pCap->gpio_mask = AR_GPIO_MASK;
2486 struct ath9k_hw_capabilities *pCap = &ah->caps;
2513 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
2520 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
2523 if ((pCap->hw_caps & (ATH9K_HW_CAP_2GHZ | ATH9K_HW_CAP_5GHZ)) == 0) {
2534 pCap->chip_chainmask = 1;
2536 pCap->chip_chainmask = 7;
2541 pCap->chip_chainmask = 3;
2543 pCap->chip_chainmask = 7;
2545 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2554 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2556 pCap->rx_chainmask = 0x7;
2559 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2561 pCap->tx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->tx_chainmask);
2562 pCap->rx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->rx_chainmask);
2563 ah->txchainmask = pCap->tx_chainmask;
2564 ah->rxchainmask = pCap->rx_chainmask;
2575 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2577 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2580 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2582 pCap->rts_aggr_limit = (8 * 1024);
2592 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2596 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2598 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2601 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2603 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2606 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
2609 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2611 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2612 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2613 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2614 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2615 pCap->txs_len = sizeof(struct ar9003_txs);
2617 pCap->tx_desc_len = sizeof(struct ath_desc);
2619 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2623 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2631 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2638 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2646 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2652 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2658 pCap->hw_caps |= ATH9K_HW_CAP_DFS;
2660 tx_chainmask = pCap->tx_chainmask;
2661 rx_chainmask = pCap->rx_chainmask;
2664 pCap->max_txchains++;
2666 pCap->max_rxchains++;
2674 pCap->hw_caps |= ATH9K_HW_CAP_MCI;
2677 pCap->hw_caps |= ATH9K_HW_CAP_RTT;
2682 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;