Lines Matching defs:pipe
764 static int __ath10k_pci_rx_post_buf(struct ath10k_pci_pipe *pipe)
766 struct ath10k *ar = pipe->hif_ce_state;
768 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
773 skb = dev_alloc_skb(pipe->buf_sz);
803 static void ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe *pipe)
805 struct ath10k *ar = pipe->hif_ce_state;
808 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
811 if (pipe->buf_sz == 0)
822 ret = __ath10k_pci_rx_post_buf(pipe);
1222 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n",
1271 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n",
1298 /* CE4 polling needs to be done whenever CE pipe which transports
1341 /* CE4 polling needs to be done whenever CE pipe which transports
1425 u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe)
1431 return ath10k_ce_num_free_src_entries(ar_pci->pipe_info[pipe].ce_hdl);
1787 void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe,
1803 resources = ath10k_pci_hif_get_free_queue_number(ar, pipe);
1809 if (resources > (ar_pci->attr[pipe].src_nentries >> 1))
1812 ath10k_ce_per_engine_service(ar, pipe);
1871 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get default pipe\n");
2359 ath10k_err(ar, "Failed to get pipe cfg addr: %d\n", ret);
2365 ath10k_err(ar, "Invalid pipe cfg addr\n");
2375 ath10k_err(ar, "Failed to write pipe cfg: %d\n", ret);
2384 ath10k_err(ar, "Failed to get svc/pipe map: %d\n", ret);
2398 ath10k_err(ar, "Failed to write svc/pipe map: %d\n", ret);
2491 struct ath10k_pci_pipe *pipe;
2496 pipe = &ar_pci->pipe_info[i];
2497 pipe->ce_hdl = &ce->ce_states[i];
2498 pipe->pipe_num = i;
2499 pipe->hif_ce_state = ar;
2503 ath10k_err(ar, "failed to allocate copy engine pipe %d: %d\n",
2510 ar_pci->ce_diag = pipe->ce_hdl;
2514 pipe->buf_sz = (size_t)(ar_pci->attr[i].src_sz_max);
2536 ath10k_err(ar, "failed to initialize copy engine pipe %d: %d\n",