Lines Matching defs:htt
21 #include "htt.h"
3588 lockdep_assert_held(&ar->htt.tx_lock);
3609 lockdep_assert_held(&ar->htt.tx_lock);
3629 lockdep_assert_held(&ar->htt.tx_lock);
3640 lockdep_assert_held(&ar->htt.tx_lock);
3660 lockdep_assert_held(&ar->htt.tx_lock);
3705 spin_lock_bh(&ar->htt.tx_lock);
3710 spin_unlock_bh(&ar->htt.tx_lock);
3748 if (ar->htt.target_version_major < 3 &&
3950 return (ar->htt.target_version_major >= 3 &&
3951 ar->htt.target_version_minor >= 4 &&
3986 else if (ar->htt.target_version_major >= 3)
4000 struct ath10k_htt *htt = &ar->htt;
4005 ret = ath10k_htt_tx(htt, txmode, skb);
4008 ret = ath10k_htt_mgmt_tx(htt, skb);
4278 spin_lock_bh(&ar->htt.tx_lock);
4279 idr_for_each_entry(&ar->htt.pending_tx, msdu, msdu_id) {
4284 spin_unlock_bh(&ar->htt.tx_lock);
4317 if (ar->htt.tx_q_state.mode == HTT_TX_MODE_SWITCH_PUSH)
4320 if (ar->htt.num_pending_tx < ar->htt.tx_q_state.num_push_allowed)
4379 struct ath10k_htt *htt = &ar->htt;
4392 spin_lock_bh(&ar->htt.tx_lock);
4393 ret = ath10k_htt_tx_inc_pending(htt);
4394 spin_unlock_bh(&ar->htt.tx_lock);
4401 spin_lock_bh(&ar->htt.tx_lock);
4402 ath10k_htt_tx_dec_pending(htt);
4403 spin_unlock_bh(&ar->htt.tx_lock);
4420 spin_lock_bh(&ar->htt.tx_lock);
4421 ret = ath10k_htt_tx_mgmt_inc_pending(htt, is_mgmt, is_presp);
4424 ath10k_htt_tx_dec_pending(htt);
4425 spin_unlock_bh(&ar->htt.tx_lock);
4428 spin_unlock_bh(&ar->htt.tx_lock);
4435 spin_lock_bh(&ar->htt.tx_lock);
4436 ath10k_htt_tx_dec_pending(htt);
4438 ath10k_htt_tx_mgmt_dec_pending(htt);
4439 spin_unlock_bh(&ar->htt.tx_lock);
4444 spin_lock_bh(&ar->htt.tx_lock);
4446 spin_unlock_bh(&ar->htt.tx_lock);
4478 if (ar->htt.tx_q_state.mode != HTT_TX_MODE_SWITCH_PUSH)
4481 if (ar->htt.num_pending_tx >= (ar->htt.max_num_pending_tx / 2))
4664 struct ath10k_htt *htt = &ar->htt;
4688 spin_lock_bh(&ar->htt.tx_lock);
4695 ret = ath10k_htt_tx_inc_pending(htt);
4699 spin_unlock_bh(&ar->htt.tx_lock);
4704 ret = ath10k_htt_tx_mgmt_inc_pending(htt, is_mgmt, is_presp);
4708 ath10k_htt_tx_dec_pending(htt);
4709 spin_unlock_bh(&ar->htt.tx_lock);
4713 spin_unlock_bh(&ar->htt.tx_lock);
4720 spin_lock_bh(&ar->htt.tx_lock);
4721 ath10k_htt_tx_dec_pending(htt);
4723 ath10k_htt_tx_mgmt_dec_pending(htt);
4724 spin_unlock_bh(&ar->htt.tx_lock);
4738 if (ar->htt.tx_q_state.mode != HTT_TX_MODE_SWITCH_PUSH)
5852 spin_lock_bh(&ar->htt.tx_lock);
5855 spin_unlock_bh(&ar->htt.tx_lock);
6003 spin_lock_bh(&ar->htt.tx_lock);
6005 spin_unlock_bh(&ar->htt.tx_lock);
8055 time_left = wait_event_timeout(ar->htt.empty_tx_wq, ({
8058 spin_lock_bh(&ar->htt.tx_lock);
8059 empty = (ar->htt.num_pending_tx == 0);
8060 spin_unlock_bh(&ar->htt.tx_lock);
8089 ath10k_htt_flush_tx(&ar->htt);
9339 if (ar->htt.disable_tx_comp) {