Lines Matching defs:REGBASE
88 REGBASE = DPRBASE + 0x1000
89 PICR = REGBASE + 0x026 // 16-bit periodic irq control
90 PITR = REGBASE + 0x02A // 16-bit periodic irq timing
91 OR1 = REGBASE + 0x064 // 32-bit RAM bank #1 options
92 CICR = REGBASE + 0x540 // 32(24)-bit CP interrupt config
93 CIMR = REGBASE + 0x548 // 32-bit CP interrupt mask
94 CISR = REGBASE + 0x54C // 32-bit CP interrupts in-service
95 PADIR = REGBASE + 0x550 // 16-bit PortA data direction bitmap
96 PAPAR = REGBASE + 0x552 // 16-bit PortA pin assignment bitmap
97 PAODR = REGBASE + 0x554 // 16-bit PortA open drain bitmap
98 PADAT = REGBASE + 0x556 // 16-bit PortA data register
100 PCDIR = REGBASE + 0x560 // 16-bit PortC data direction bitmap
101 PCPAR = REGBASE + 0x562 // 16-bit PortC pin assignment bitmap
102 PCSO = REGBASE + 0x564 // 16-bit PortC special options
103 PCDAT = REGBASE + 0x566 // 16-bit PortC data register
104 PCINT = REGBASE + 0x568 // 16-bit PortC interrupt control
105 CR = REGBASE + 0x5C0 // 16-bit Command register
107 SCC1_REGS = REGBASE + 0x600
108 SCC2_REGS = REGBASE + 0x620
109 SCC3_REGS = REGBASE + 0x640
110 SCC4_REGS = REGBASE + 0x660
111 SICR = REGBASE + 0x6EC // 32-bit SI clock route