Lines Matching defs:rate
113 /* Data rate is full (default) or half the configured clk speed */
195 * frequency (= clock rate) is 4 / 142.5 ns = 28.07 MHz (Mb/s).
196 * (max specified clock rate for IXP42x HSS is 8.192 Mb/s).
1231 static u32 check_clock(u32 timer_freq, u32 rate, u32 a, u32 b, u32 c,
1240 new_diff = abs((u32)new_rate - rate);
1250 static void find_best_clock(u32 timer_freq, u32 rate, u32 *best, u32 *reg)
1254 a = timer_freq / rate;
1257 check_clock(timer_freq, rate, 0x3FF, 1, 1, best, &diff, reg);
1262 rate = timer_freq;
1265 if (rate * a == timer_freq) { /* don't divide by 0 later */
1266 check_clock(timer_freq, rate, a - 1, 1, 1, best, &diff, reg);
1271 u64 c = (b + 1) * (u64)rate;
1273 do_div(c, timer_freq - rate * a);
1276 if (b == 0 && /* also try a bit higher rate */
1277 !check_clock(timer_freq, rate, a - 1, 1, 1, best,
1280 check_clock(timer_freq, rate, a, b, 0xFFF, best,
1284 if (!check_clock(timer_freq, rate, a, b, c, best, &diff, reg))
1286 if (!check_clock(timer_freq, rate, a, b, c + 1, best, &diff,