Lines Matching defs:port
3 * Intel IXP4xx HSS (synchronous serial port) driver for Linux
206 #define HSS_CONFIG_TX_PCR 0x00 /* port configuration registers */
258 struct port {
325 #define rx_desc_phys(port, n) ((port)->desc_tab_phys + \
327 #define rx_desc_ptr(port, n) (&(port)->desc_tab[n])
329 #define tx_desc_phys(port, n) ((port)->desc_tab_phys + \
331 #define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])
345 static inline struct port *dev_to_port(struct net_device *dev)
364 static void hss_npe_send(struct port *port, struct msg *msg, const char *what)
368 if (npe_send_message(port->npe, msg, what)) {
370 port->id, val[0], val[1], npe_name(port->npe));
375 static void hss_config_set_lut(struct port *port)
382 msg.hss_port = port->id;
390 hss_npe_send(port, &msg, "HSS_SET_TX_LUT");
393 hss_npe_send(port, &msg, "HSS_SET_RX_LUT");
398 static void hss_config(struct port *port)
404 msg.hss_port = port->id;
408 if (port->clock_type == CLOCK_INT)
410 hss_npe_send(port, &msg, "HSS_SET_TX_PCR");
414 hss_npe_send(port, &msg, "HSS_SET_RX_PCR");
418 msg.hss_port = port->id;
420 msg.data32 = (port->loopback ? CCR_LOOPBACK : 0) |
421 (port->id ? CCR_SECOND_HSS : 0);
422 hss_npe_send(port, &msg, "HSS_SET_CORE_CR");
426 msg.hss_port = port->id;
428 msg.data32 = port->clock_reg;
429 hss_npe_send(port, &msg, "HSS_SET_CLOCK_CR");
433 msg.hss_port = port->id;
437 hss_npe_send(port, &msg, "HSS_SET_TX_FCR");
441 msg.hss_port = port->id;
445 hss_npe_send(port, &msg, "HSS_SET_RX_FCR");
447 hss_config_set_lut(port);
451 msg.hss_port = port->id;
452 hss_npe_send(port, &msg, "HSS_LOAD_CONFIG");
454 if (npe_recv_message(port->npe, &msg, "HSS_LOAD_CONFIG") ||
455 /* HSS_LOAD_CONFIG for port #1 returns port_id = #4 */
457 pr_crit("HSS-%i: HSS_LOAD_CONFIG failed\n", port->id);
462 npe_recv_message(port->npe, &msg, "FLUSH_IT");
465 static void hss_set_hdlc_cfg(struct port *port)
471 msg.hss_port = port->id;
472 msg.data8a = port->hdlc_cfg; /* rx_cfg */
473 msg.data8b = port->hdlc_cfg | (PKT_EXTRA_FLAGS << 3); /* tx_cfg */
474 hss_npe_send(port, &msg, "HSS_SET_HDLC_CFG");
477 static u32 hss_get_status(struct port *port)
483 msg.hss_port = port->id;
484 hss_npe_send(port, &msg, "PORT_ERROR_READ");
485 if (npe_recv_message(port->npe, &msg, "PORT_ERROR_READ")) {
486 pr_crit("HSS-%i: unable to read HSS status\n", port->id);
493 static void hss_start_hdlc(struct port *port)
499 msg.hss_port = port->id;
501 hss_npe_send(port, &msg, "HSS_ENABLE_PKT_PIPE");
504 static void hss_stop_hdlc(struct port *port)
510 msg.hss_port = port->id;
511 hss_npe_send(port, &msg, "HSS_DISABLE_PKT_PIPE");
512 hss_get_status(port); /* make sure it's halted */
515 static int hss_load_firmware(struct port *port)
520 if (port->initialized)
523 if (!npe_running(port->npe)) {
524 err = npe_load_firmware(port->npe, npe_name(port->npe),
525 port->dev);
533 msg.hss_port = port->id;
535 hss_npe_send(port, &msg, "HSS_SET_PKT_PIPES");
539 hss_npe_send(port, &msg, "HSS_SET_PKT_FIFO");
545 hss_npe_send(port, &msg, "HSS_SET_PKT_MODE");
549 hss_npe_send(port, &msg, "HSS_SET_PKT_RX_SIZE");
553 hss_npe_send(port, &msg, "HSS_SET_PKT_IDLE");
555 port->initialized = 1;
588 static inline int queue_get_desc(unsigned int queue, struct port *port,
599 tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
600 tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
619 static inline void dma_unmap_tx(struct port *port, struct desc *desc)
622 dma_unmap_single(&port->netdev->dev, desc->data,
625 dma_unmap_single(&port->netdev->dev, desc->data & ~3,
634 struct port *port = dev_to_port(netdev);
638 port->carrier = carrier;
639 if (!port->loopback) {
651 struct port *port = dev_to_port(dev);
656 qmgr_disable_irq(port->rxq);
657 napi_schedule(&port->napi);
662 struct port *port = container_of(napi, struct port, napi);
663 struct net_device *dev = port->netdev;
664 unsigned int rxq = port->rxq;
665 unsigned int rxfreeq = port->rxfreeq;
681 n = queue_get_desc(rxq, port, 0);
706 desc = rx_desc_ptr(port, n);
756 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
763 skb = port->rx_buff_tab[n];
769 memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
783 port->rx_buff_tab[n] = temp;
788 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
800 struct port *port = dev_to_port(dev);
806 while ((n_desc = queue_get_desc(port->txdoneq,
807 port, 1)) >= 0) {
811 desc = tx_desc_ptr(port, n_desc);
816 dma_unmap_tx(port, desc);
819 dev->name, port->tx_buff_tab[n_desc]);
821 free_buffer_irq(port->tx_buff_tab[n_desc]);
822 port->tx_buff_tab[n_desc] = NULL;
824 start = qmgr_stat_below_low_watermark(port->txreadyq);
825 queue_put_desc(port->txreadyq,
826 tx_desc_phys(port, n_desc), desc);
839 struct port *port = dev_to_port(dev);
840 unsigned int txreadyq = port->txreadyq;
887 n = queue_get_desc(txreadyq, port, 1);
889 desc = tx_desc_ptr(port, n);
892 port->tx_buff_tab[n] = skb;
894 port->tx_buff_tab[n] = mem;
900 queue_put_desc(port->txq, tx_desc_phys(port, n), desc);
923 static int request_hdlc_queues(struct port *port)
927 err = qmgr_request_queue(port->rxfreeq, RX_DESCS, 0, 0,
928 "%s:RX-free", port->netdev->name);
932 err = qmgr_request_queue(port->rxq, RX_DESCS, 0, 0,
933 "%s:RX", port->netdev->name);
937 err = qmgr_request_queue(port->txq, TX_DESCS, 0, 0,
938 "%s:TX", port->netdev->name);
942 err = qmgr_request_queue(port->txreadyq, TX_DESCS, 0, 0,
943 "%s:TX-ready", port->netdev->name);
947 err = qmgr_request_queue(port->txdoneq, TX_DESCS, 0, 0,
948 "%s:TX-done", port->netdev->name);
954 qmgr_release_queue(port->txreadyq);
956 qmgr_release_queue(port->txq);
958 qmgr_release_queue(port->rxq);
960 qmgr_release_queue(port->rxfreeq);
962 port->netdev->name);
966 static void release_hdlc_queues(struct port *port)
968 qmgr_release_queue(port->rxfreeq);
969 qmgr_release_queue(port->rxq);
970 qmgr_release_queue(port->txdoneq);
971 qmgr_release_queue(port->txq);
972 qmgr_release_queue(port->txreadyq);
975 static int init_hdlc_queues(struct port *port)
980 dma_pool = dma_pool_create(DRV_NAME, &port->netdev->dev,
986 port->desc_tab = dma_pool_zalloc(dma_pool, GFP_KERNEL,
987 &port->desc_tab_phys);
988 if (!port->desc_tab)
990 memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
991 memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
995 struct desc *desc = rx_desc_ptr(port, i);
999 buff = netdev_alloc_skb(port->netdev, RX_SIZE);
1010 desc->data = dma_map_single(&port->netdev->dev, data,
1012 if (dma_mapping_error(&port->netdev->dev, desc->data)) {
1016 port->rx_buff_tab[i] = buff;
1022 static void destroy_hdlc_queues(struct port *port)
1026 if (port->desc_tab) {
1028 struct desc *desc = rx_desc_ptr(port, i);
1029 buffer_t *buff = port->rx_buff_tab[i];
1032 dma_unmap_single(&port->netdev->dev,
1039 struct desc *desc = tx_desc_ptr(port, i);
1040 buffer_t *buff = port->tx_buff_tab[i];
1043 dma_unmap_tx(port, desc);
1047 dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
1048 port->desc_tab = NULL;
1060 struct port *port = dev_to_port(dev);
1063 val = gpiod_get_value(port->dcd);
1071 struct port *port = dev_to_port(dev);
1080 err = hss_load_firmware(port);
1084 err = request_hdlc_queues(port);
1088 err = init_hdlc_queues(port);
1097 val = gpiod_get_value(port->dcd);
1101 err = request_irq(gpiod_to_irq(port->dcd), hss_hdlc_dcd_irq, 0, "IXP4xx HSS", dev);
1108 gpiod_set_value(port->dtr, 1);
1109 gpiod_set_value(port->rts, 1);
1115 queue_put_desc(port->txreadyq,
1116 tx_desc_phys(port, i), tx_desc_ptr(port, i));
1119 queue_put_desc(port->rxfreeq,
1120 rx_desc_phys(port, i), rx_desc_ptr(port, i));
1122 napi_enable(&port->napi);
1125 qmgr_set_irq(port->rxq, QUEUE_IRQ_SRC_NOT_EMPTY,
1128 qmgr_set_irq(port->txdoneq, QUEUE_IRQ_SRC_NOT_EMPTY,
1130 qmgr_enable_irq(port->txdoneq);
1134 hss_set_hdlc_cfg(port);
1135 hss_config(port);
1137 hss_start_hdlc(port);
1140 napi_schedule(&port->napi);
1146 destroy_hdlc_queues(port);
1147 release_hdlc_queues(port);
1155 struct port *port = dev_to_port(dev);
1161 qmgr_disable_irq(port->rxq);
1163 napi_disable(&port->napi);
1165 hss_stop_hdlc(port);
1167 while (queue_get_desc(port->rxfreeq, port, 0) >= 0)
1169 while (queue_get_desc(port->rxq, port, 0) >= 0)
1177 while (queue_get_desc(port->txq, port, 1) >= 0)
1182 while (queue_get_desc(port->txreadyq, port, 1) >= 0)
1195 qmgr_disable_irq(port->txdoneq);
1197 free_irq(gpiod_to_irq(port->dcd), dev);
1199 gpiod_set_value(port->dtr, 0);
1200 gpiod_set_value(port->rts, 0);
1203 destroy_hdlc_queues(port);
1204 release_hdlc_queues(port);
1212 struct port *port = dev_to_port(dev);
1219 port->hdlc_cfg = 0;
1223 port->hdlc_cfg = PKT_HDLC_CRC_32;
1292 static int hss_hdlc_set_clock(struct port *port, unsigned int clock_type)
1297 gpiod_set_value(port->clk_internal, 0);
1300 gpiod_set_value(port->clk_internal, 1);
1312 struct port *port = dev_to_port(dev);
1324 new_line.clock_type = port->clock_type;
1325 new_line.clock_rate = port->clock_rate;
1326 new_line.loopback = port->loopback;
1339 hss_hdlc_set_clock(port, clk);
1347 port->clock_type = clk; /* Update settings */
1351 &port->clock_rate, &port->clock_reg);
1353 port->clock_rate = 0;
1354 port->clock_reg = CLK42X_SPEED_2048KHZ;
1356 port->loopback = new_line.loopback;
1361 hss_config(port);
1363 if (port->loopback || port->carrier)
1364 netif_carrier_on(port->netdev);
1366 netif_carrier_off(port->netdev);
1395 struct port *port;
1419 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
1420 if (!port)
1428 port->npe = npe_request(npe_spec.args[0] << 4);
1429 if (!port->npe) {
1439 port->txreadyq = queue_spec.args[0];
1445 port->rxtrigq = queue_spec.args[0];
1451 port->rxq = queue_spec.args[0];
1457 port->txq = queue_spec.args[0];
1463 port->rxfreeq = queue_spec.args[0];
1469 port->txdoneq = queue_spec.args[0];
1472 port->cts = devm_gpiod_get(dev, "cts", GPIOD_OUT_LOW);
1473 if (IS_ERR(port->cts))
1474 return dev_err_probe(dev, PTR_ERR(port->cts), "unable to get CTS GPIO\n");
1475 port->rts = devm_gpiod_get(dev, "rts", GPIOD_OUT_LOW);
1476 if (IS_ERR(port->rts))
1477 return dev_err_probe(dev, PTR_ERR(port->rts), "unable to get RTS GPIO\n");
1478 port->dcd = devm_gpiod_get(dev, "dcd", GPIOD_IN);
1479 if (IS_ERR(port->dcd))
1480 return dev_err_probe(dev, PTR_ERR(port->dcd), "unable to get DCD GPIO\n");
1481 port->dtr = devm_gpiod_get(dev, "dtr", GPIOD_OUT_LOW);
1482 if (IS_ERR(port->dtr))
1483 return dev_err_probe(dev, PTR_ERR(port->dtr), "unable to get DTR GPIO\n");
1484 port->clk_internal = devm_gpiod_get(dev, "clk-internal", GPIOD_OUT_LOW);
1485 if (IS_ERR(port->clk_internal))
1486 return dev_err_probe(dev, PTR_ERR(port->clk_internal),
1489 ndev = alloc_hdlcdev(port);
1490 port->netdev = alloc_hdlcdev(port);
1491 if (!port->netdev) {
1502 port->clock_type = CLOCK_EXT;
1503 port->clock_rate = 0;
1504 port->clock_reg = CLK42X_SPEED_2048KHZ;
1505 port->id = pdev->id;
1506 port->dev = &pdev->dev;
1507 netif_napi_add_weight(ndev, &port->napi, hss_hdlc_poll, NAPI_WEIGHT);
1513 platform_set_drvdata(pdev, port);
1521 npe_release(port->npe);
1527 struct port *port = platform_get_drvdata(pdev);
1529 unregister_hdlc_device(port->netdev);
1530 free_netdev(port->netdev);
1531 npe_release(port->npe);