Lines Matching defs:clk
99 /* Frame sync pin: input (default) or output generated off a given clk edge */
113 /* Data rate is full (default) or half the configured clk speed */
1314 int clk;
1338 clk = new_line.clock_type;
1339 hss_hdlc_set_clock(port, clk);
1341 if (clk != CLOCK_EXT && clk != CLOCK_INT)
1347 port->clock_type = clk; /* Update settings */
1348 if (clk == CLOCK_INT) {
1484 port->clk_internal = devm_gpiod_get(dev, "clk-internal", GPIOD_OUT_LOW);