Lines Matching defs:val
824 u32 val;
828 ret = lan78xx_read_reg(dev, MII_ACC, &val);
832 if (!(val & MII_ACC_MII_BUSY_))
857 u32 val;
861 ret = lan78xx_read_reg(dev, E2P_CMD, &val);
865 if (!(val & E2P_CMD_EPC_BUSY_) ||
866 (val & E2P_CMD_EPC_TIMEOUT_))
871 if (val & (E2P_CMD_EPC_TIMEOUT_ | E2P_CMD_EPC_BUSY_)) {
882 u32 val;
886 ret = lan78xx_read_reg(dev, E2P_CMD, &val);
890 if (!(val & E2P_CMD_EPC_BUSY_))
903 u32 val;
911 ret = lan78xx_read_reg(dev, HW_CFG, &val);
912 saved = val;
914 val &= ~(HW_CFG_LED1_EN_ | HW_CFG_LED0_EN_);
915 ret = lan78xx_write_reg(dev, HW_CFG, val);
923 val = E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_READ_;
924 val |= (offset & E2P_CMD_EPC_ADDR_MASK_);
925 ret = lan78xx_write_reg(dev, E2P_CMD, val);
935 ret = lan78xx_read_reg(dev, E2P_DATA, &val);
941 data[i] = val & 0xFF;
971 u32 val;
979 ret = lan78xx_read_reg(dev, HW_CFG, &val);
980 saved = val;
982 val &= ~(HW_CFG_LED1_EN_ | HW_CFG_LED0_EN_);
983 ret = lan78xx_write_reg(dev, HW_CFG, val);
991 val = E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_EWEN_;
992 ret = lan78xx_write_reg(dev, E2P_CMD, val);
1004 val = data[i];
1005 ret = lan78xx_write_reg(dev, E2P_DATA, val);
1012 val = E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_WRITE_;
1013 val |= (offset & E2P_CMD_EPC_ADDR_MASK_);
1014 ret = lan78xx_write_reg(dev, E2P_CMD, val);
1374 u32 val;
1387 ret = lan78xx_read_reg(dev, MAC_CR, &val);
1391 val |= MAC_CR_RST_;
1392 ret = lan78xx_write_reg(dev, MAC_CR, val);
1400 ret = lan78xx_read_reg(dev, MAC_CR, &val);
1404 if (!(val & MAC_CR_RST_)) {
1996 u32 val, addr;
2018 ret = lan78xx_read_reg(dev, MII_DATA, &val);
2020 ret = (int)(val & 0xFFFF);
2033 u32 val, addr;
2047 val = (u32)regval;
2048 ret = lan78xx_write_reg(dev, MII_DATA, val);