Lines Matching refs:ret
111 int bt1_ctrl, ctrl1, ctrl2, ret;
167 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, ctrl1);
168 if (ret < 0)
169 return ret;
171 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2, ctrl2);
172 if (ret < 0)
173 return ret;
176 ret = genphy_c45_pma_baset1_setup_master_slave(phydev);
177 if (ret < 0)
178 return ret;
184 ret = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL,
186 if (ret < 0)
187 return ret;
207 int ret;
238 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L,
240 if (ret < 0)
241 return ret;
242 if (ret > 0)
247 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M,
249 if (ret < 0)
250 return ret;
251 if (ret > 0)
268 int changed = 0, ret;
274 ret = genphy_c45_an_config_eee_aneg(phydev);
275 if (ret < 0)
276 return ret;
277 else if (ret)
285 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE,
289 if (ret < 0)
290 return ret;
291 if (ret > 0)
296 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
300 if (ret < 0)
301 return ret;
302 if (ret > 0)
362 int ret;
369 ret = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
370 if (ret < 0)
371 return ret;
373 if (!(ret & MDIO_AN_CTRL1_ENABLE))
1041 int ret;
1047 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L);
1048 if (ret < 0)
1049 return ret;
1055 if (ret & MDIO_AN_T1_ADV_L_FORCE_MS) {
1079 int ret;
1081 ret = genphy_c45_read_link(phydev);
1082 if (ret)
1083 return ret;
1091 ret = genphy_c45_read_lpa(phydev);
1092 if (ret)
1093 return ret;
1096 ret = genphy_c45_baset1_read_status(phydev);
1097 if (ret < 0)
1098 return ret;
1103 ret = genphy_c45_read_pma(phydev);
1106 return ret;
1121 int ret;
1126 ret = genphy_c45_an_config_aneg(phydev);
1127 if (ret < 0)
1128 return ret;
1129 if (ret > 0)
1164 int ret;
1171 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
1173 if (ret)
1174 return ret;
1176 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_CTRL2,
1178 if (ret)
1179 return ret;
1199 int ret;
1201 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_IDVER);
1202 if (ret < 0)
1203 return ret;
1205 if ((ret & MDIO_OATC14_PLCA_IDM) != OATC14_IDM)
1208 plca_cfg->version = ret & ~MDIO_OATC14_PLCA_IDM;
1210 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_CTRL0);
1211 if (ret < 0)
1212 return ret;
1214 plca_cfg->enabled = !!(ret & MDIO_OATC14_PLCA_EN);
1216 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_CTRL1);
1217 if (ret < 0)
1218 return ret;
1220 plca_cfg->node_cnt = (ret & MDIO_OATC14_PLCA_NCNT) >> 8;
1221 plca_cfg->node_id = (ret & MDIO_OATC14_PLCA_ID);
1223 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_TOTMR);
1224 if (ret < 0)
1225 return ret;
1227 plca_cfg->to_tmr = ret & MDIO_OATC14_PLCA_TOT;
1229 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_BURST);
1230 if (ret < 0)
1231 return ret;
1233 plca_cfg->burst_cnt = (ret & MDIO_OATC14_PLCA_MAXBC) >> 8;
1234 plca_cfg->burst_tmr = (ret & MDIO_OATC14_PLCA_BTMR);
1254 int ret;
1262 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,
1266 if (ret < 0)
1267 return ret;
1277 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2,
1280 if (ret < 0)
1281 return ret;
1283 val = ret;
1294 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
1297 if (ret < 0)
1298 return ret;
1302 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
1306 if (ret < 0)
1307 return ret;
1317 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2,
1320 if (ret < 0)
1321 return ret;
1323 val = ret;
1334 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
1337 if (ret < 0)
1338 return ret;
1343 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
1347 if (ret < 0)
1348 return ret;
1367 int ret;
1369 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_STATUS);
1370 if (ret < 0)
1371 return ret;
1373 plca_st->pst = !!(ret & MDIO_OATC14_PLCA_PST);
1395 int ret;
1397 ret = genphy_c45_read_eee_adv(phydev, tmp_adv);
1398 if (ret)
1399 return ret;
1401 ret = genphy_c45_read_eee_lpa(phydev, tmp_lp);
1402 if (ret)
1403 return ret;
1438 int ret;
1440 ret = genphy_c45_eee_is_active(phydev, adv, lp, &is_enabled);
1441 if (ret < 0)
1442 return ret;
1445 data->eee_active = ret;
1476 int ret;
1502 ret = genphy_c45_an_config_eee_aneg(phydev);
1503 if (ret < 0)
1504 return ret;
1505 if (ret > 0)