Lines Matching defs:phydev
15 * @phydev: target phy_device struct
17 static bool genphy_c45_baset1_able(struct phy_device *phydev)
21 if (phydev->pma_extable == -ENODATA) {
22 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE);
26 phydev->pma_extable = val;
29 return !!(phydev->pma_extable & MDIO_PMA_EXTABLE_BT1);
34 * @phydev: target phy_device struct
36 static bool genphy_c45_pma_can_sleep(struct phy_device *phydev)
40 stat1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT1);
49 * @phydev: target phy_device struct
51 int genphy_c45_pma_resume(struct phy_device *phydev)
53 if (!genphy_c45_pma_can_sleep(phydev))
56 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
63 * @phydev: target phy_device struct
65 int genphy_c45_pma_suspend(struct phy_device *phydev)
67 if (!genphy_c45_pma_can_sleep(phydev))
70 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
78 * @phydev: target phy_device struct
80 int genphy_c45_pma_baset1_setup_master_slave(struct phy_device *phydev)
84 switch (phydev->master_slave_set) {
96 phydev_warn(phydev, "Unsupported Master/Slave mode\n");
100 return phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL,
107 * @phydev: target phy_device struct
109 int genphy_c45_pma_setup_forced(struct phy_device *phydev)
114 if (phydev->duplex != DUPLEX_FULL)
117 ctrl1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1);
121 ctrl2 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2);
132 switch (phydev->speed) {
134 if (genphy_c45_baset1_able(phydev))
167 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, ctrl1);
171 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2, ctrl2);
175 if (genphy_c45_baset1_able(phydev)) {
176 ret = genphy_c45_pma_baset1_setup_master_slave(phydev);
181 if (phydev->speed == SPEED_1000)
184 ret = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL,
190 return genphy_c45_an_disable_aneg(phydev);
202 static int genphy_c45_baset1_an_config_aneg(struct phy_device *phydev)
213 switch (phydev->master_slave_set) {
232 phydev_warn(phydev, "Unsupported Master/Slave mode\n");
236 adv_l |= linkmode_adv_to_mii_t1_adv_l_t(phydev->advertising);
238 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L,
245 adv_m |= linkmode_adv_to_mii_t1_adv_m_t(phydev->advertising);
247 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M,
259 * @phydev: target phy_device struct
261 * Configure advertisement registers based on modes set in phydev->advertising
266 int genphy_c45_an_config_aneg(struct phy_device *phydev)
271 linkmode_and(phydev->advertising, phydev->advertising,
272 phydev->supported);
274 ret = genphy_c45_an_config_eee_aneg(phydev);
280 if (genphy_c45_baset1_able(phydev))
281 return genphy_c45_baset1_an_config_aneg(phydev);
283 adv = linkmode_adv_to_mii_adv_t(phydev->advertising);
285 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE,
294 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising);
296 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
311 * @phydev: target phy_device struct
318 int genphy_c45_an_disable_aneg(struct phy_device *phydev)
322 if (genphy_c45_baset1_able(phydev))
325 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
332 * @phydev: target phy_device struct
338 int genphy_c45_restart_aneg(struct phy_device *phydev)
342 if (genphy_c45_baset1_able(phydev))
345 return phy_set_bits_mmd(phydev, MDIO_MMD_AN, reg,
352 * @phydev: target phy_device struct
359 int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart)
364 if (genphy_c45_baset1_able(phydev))
369 ret = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
378 return genphy_c45_restart_aneg(phydev);
386 * @phydev: target phy_device struct
395 int genphy_c45_aneg_done(struct phy_device *phydev)
400 if (genphy_c45_baset1_able(phydev))
403 val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
411 * @phydev: target phy_device struct
414 * that the link is up, set phydev->link to 1. If an error is encountered,
417 int genphy_c45_read_link(struct phy_device *phydev)
423 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) {
424 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
432 phydev->link = 0;
446 if (!phy_polling_mode(phydev) || !phydev->link) {
447 val = phy_read_mmd(phydev, devad, MDIO_STAT1);
454 val = phy_read_mmd(phydev, devad, MDIO_STAT1);
462 phydev->link = link;
471 * pause and asym_pause members in phydev.
473 static int genphy_c45_baset1_read_lpa(struct phy_device *phydev)
477 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT);
482 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising);
483 mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, 0);
484 mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, 0);
486 phydev->pause = 0;
487 phydev->asym_pause = 0;
492 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising, 1);
494 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_L);
498 mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, val);
499 phydev->pause = val & MDIO_AN_T1_ADV_L_PAUSE_CAP ? 1 : 0;
500 phydev->asym_pause = val & MDIO_AN_T1_ADV_L_PAUSE_ASYM ? 1 : 0;
502 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_M);
506 mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, val);
513 * @phydev: target phy_device struct
517 * in @phydev. This assumes that the auto-negotiation MMD is present, and
521 int genphy_c45_read_lpa(struct phy_device *phydev)
525 if (genphy_c45_baset1_able(phydev))
526 return genphy_c45_baset1_read_lpa(phydev);
528 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
534 phydev->lp_advertising);
535 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0);
536 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, 0);
537 phydev->pause = 0;
538 phydev->asym_pause = 0;
543 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising,
547 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA);
551 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, val);
552 phydev->pause = val & LPA_PAUSE_CAP ? 1 : 0;
553 phydev->asym_pause = val & LPA_PAUSE_ASYM ? 1 : 0;
556 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
560 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, val);
569 * @phydev: target phy_device struct
571 int genphy_c45_pma_baset1_read_master_slave(struct phy_device *phydev)
575 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
576 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
578 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL);
583 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
584 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
586 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
587 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
596 * @phydev: target phy_device struct
598 int genphy_c45_read_pma(struct phy_device *phydev)
602 linkmode_zero(phydev->lp_advertising);
604 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1);
610 phydev->speed = SPEED_10;
613 phydev->speed = SPEED_100;
616 phydev->speed = SPEED_1000;
619 phydev->speed = SPEED_2500;
622 phydev->speed = SPEED_5000;
625 phydev->speed = SPEED_10000;
628 phydev->speed = SPEED_UNKNOWN;
632 phydev->duplex = DUPLEX_FULL;
634 if (genphy_c45_baset1_able(phydev)) {
635 val = genphy_c45_pma_baset1_read_master_slave(phydev);
646 * @phydev: target phy_device struct
648 int genphy_c45_read_mdix(struct phy_device *phydev)
652 if (phydev->speed == SPEED_10000) {
653 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
660 phydev->mdix = ETH_TP_MDI;
664 phydev->mdix = ETH_TP_MDI_X;
668 phydev->mdix = ETH_TP_MDI_INVALID;
679 * @phydev: target phy_device struct
682 int genphy_c45_write_eee_adv(struct phy_device *phydev, unsigned long *adv)
686 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) {
692 val &= ~phydev->eee_broken_modes;
697 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN,
710 phydev->supported_eee)) {
715 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN,
730 * @phydev: target phy_device struct
733 int genphy_c45_read_eee_adv(struct phy_device *phydev, unsigned long *adv)
737 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) {
741 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
749 phydev->supported_eee)) {
753 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10BT1_AN_CTRL);
765 * @phydev: target phy_device struct
768 static int genphy_c45_read_eee_lpa(struct phy_device *phydev,
773 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) {
777 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
785 phydev->supported_eee)) {
789 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10BT1_AN_STAT);
801 * @phydev: target phy_device struct
803 static int genphy_c45_read_eee_cap1(struct phy_device *phydev)
810 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
822 mii_eee_cap1_mod_linkmode_t(phydev->supported_eee, val);
827 linkmode_and(phydev->supported_eee, phydev->supported_eee,
828 phydev->supported);
835 * @phydev: target phy_device struct
837 int genphy_c45_read_eee_abilities(struct phy_device *phydev)
845 if (linkmode_intersects(phydev->supported, PHY_EEE_CAP1_FEATURES)) {
846 val = genphy_c45_read_eee_cap1(phydev);
852 phydev->supported)) {
856 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10T1L_STAT);
861 phydev->supported_eee,
871 * @phydev: target phy_device struct
873 int genphy_c45_an_config_eee_aneg(struct phy_device *phydev)
875 if (!phydev->eee_enabled) {
878 return genphy_c45_write_eee_adv(phydev, adv);
881 return genphy_c45_write_eee_adv(phydev, phydev->advertising_eee);
886 * @phydev: target phy_device struct
890 int genphy_c45_pma_baset1_read_abilities(struct phy_device *phydev)
894 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1);
899 phydev->supported,
903 phydev->supported,
907 phydev->supported,
910 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT);
915 phydev->supported,
924 * @phydev: target phy_device struct
933 int genphy_c45_pma_read_abilities(struct phy_device *phydev)
937 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
938 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) {
939 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
945 phydev->supported);
948 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2);
953 phydev->supported,
957 phydev->supported,
961 phydev->supported,
965 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE);
970 phydev->supported,
973 phydev->supported,
976 phydev->supported,
979 phydev->supported,
982 phydev->supported,
985 phydev->supported,
989 phydev->supported,
992 phydev->supported,
996 phydev->supported,
999 phydev->supported,
1003 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
1009 phydev->supported,
1013 phydev->supported,
1018 val = genphy_c45_pma_baset1_read_abilities(phydev);
1027 genphy_c45_read_eee_abilities(phydev);
1039 int genphy_c45_baset1_read_status(struct phy_device *phydev)
1044 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
1045 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
1047 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L);
1051 cfg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M);
1057 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
1059 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
1062 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_PREFERRED;
1064 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_PREFERRED;
1073 * @phydev: target phy_device struct
1077 int genphy_c45_read_status(struct phy_device *phydev)
1081 ret = genphy_c45_read_link(phydev);
1085 phydev->speed = SPEED_UNKNOWN;
1086 phydev->duplex = DUPLEX_UNKNOWN;
1087 phydev->pause = 0;
1088 phydev->asym_pause = 0;
1090 if (phydev->autoneg == AUTONEG_ENABLE) {
1091 ret = genphy_c45_read_lpa(phydev);
1095 if (genphy_c45_baset1_able(phydev)) {
1096 ret = genphy_c45_baset1_read_status(phydev);
1101 phy_resolve_aneg_linkmode(phydev);
1103 ret = genphy_c45_read_pma(phydev);
1112 * @phydev: target phy_device struct
1118 int genphy_c45_config_aneg(struct phy_device *phydev)
1123 if (phydev->autoneg == AUTONEG_DISABLE)
1124 return genphy_c45_pma_setup_forced(phydev);
1126 ret = genphy_c45_an_config_aneg(phydev);
1132 return genphy_c45_check_and_restart_aneg(phydev, changed);
1138 int gen10g_config_aneg(struct phy_device *phydev)
1144 int genphy_c45_loopback(struct phy_device *phydev, bool enable)
1146 return phy_modify_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1,
1154 * @phydev: target phy_device struct
1162 int genphy_c45_fast_retrain(struct phy_device *phydev, bool enable)
1167 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR,
1170 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported)) {
1171 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
1176 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_CTRL2,
1182 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR,
1189 * @phydev: target phy_device struct
1196 int genphy_c45_plca_get_cfg(struct phy_device *phydev,
1201 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_IDVER);
1210 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_CTRL0);
1216 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_CTRL1);
1223 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_TOTMR);
1229 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_BURST);
1242 * @phydev: target phy_device struct
1250 int genphy_c45_plca_set_cfg(struct phy_device *phydev,
1262 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,
1277 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2,
1294 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
1302 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
1317 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2,
1334 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
1343 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
1357 * @phydev: target phy_device struct
1364 int genphy_c45_plca_get_status(struct phy_device *phydev,
1369 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_STATUS);
1380 * @phydev: target phy_device struct
1388 int genphy_c45_eee_is_active(struct phy_device *phydev, unsigned long *adv,
1397 ret = genphy_c45_read_eee_adv(phydev, tmp_adv);
1401 ret = genphy_c45_read_eee_lpa(phydev, tmp_lp);
1408 eee_active = phy_check_valid(phydev->speed, phydev->duplex,
1426 * @phydev: target phy_device struct
1432 int genphy_c45_ethtool_get_eee(struct phy_device *phydev,
1440 ret = genphy_c45_eee_is_active(phydev, adv, lp, &is_enabled);
1448 phydev->supported_eee))
1456 phydev_warn(phydev, "Not all supported or advertised EEE link modes were passed to the user space\n");
1464 * @phydev: target phy_device struct
1473 int genphy_c45_ethtool_set_eee(struct phy_device *phydev,
1484 linkmode_andnot(adv, adv, phydev->supported_eee);
1486 phydev_warn(phydev, "At least some EEE link modes are not supported.\n");
1490 ethtool_convert_legacy_u32_to_link_mode(phydev->advertising_eee,
1493 linkmode_copy(phydev->advertising_eee,
1494 phydev->supported_eee);
1497 phydev->eee_enabled = true;
1499 phydev->eee_enabled = false;
1502 ret = genphy_c45_an_config_eee_aneg(phydev);
1506 return phy_restart_aneg(phydev);