Lines Matching refs:ret
119 int ret;
121 ret = phy_modify(phydev, reg, mask, set);
122 if (ret)
123 return ret;
145 int ret;
147 ret = phy_read(phydev, MII_ECTRL);
148 if (ret < 0)
149 return ret;
151 switch (ret & MII_ECTRL_POWER_MODE_MASK) {
155 ret = phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_WAKE_REQUEST);
156 if (ret)
157 return ret;
159 ret = phy_clear_bits(phydev, MII_ECTRL, MII_ECTRL_WAKE_REQUEST);
160 if (ret)
161 return ret;
164 ret = phy_modify_check(phydev, MII_ECTRL,
167 if (ret)
168 return ret;
170 ret = phy_modify(phydev, MII_ECTRL, MII_ECTRL_POWER_MODE_MASK,
172 if (ret)
173 return ret;
175 ret = phy_modify_check(phydev, MII_GENSTAT,
178 if (ret)
179 return ret;
191 int ret;
193 ret = tja11xx_enable_reg_write(phydev);
194 if (ret)
195 return ret;
203 int ret;
212 ret = ethnl_cable_test_alloc(phydev, ETHTOOL_MSG_CABLE_TEST_NTF);
213 if (ret)
214 return ret;
216 ret = phydev->drv->cable_test_start(phydev);
217 if (ret)
218 return ret;
223 ret = phydev->drv->cable_test_get_status(phydev, &finished);
224 if (ret)
225 return ret;
235 int ret, changed = 0;
257 ret = tja11xx_config_aneg_cable_test(phydev);
258 if (ret)
259 return ret;
292 int ret;
294 ret = tja11xx_enable_reg_write(phydev);
295 if (ret)
296 return ret;
310 ret = tja11xx_get_interface_mode(phydev);
311 if (ret < 0)
312 return ret;
314 reg_val |= (ret & 0xffff);
315 ret = phy_modify(phydev, MII_CFG1, reg_mask, reg_val);
316 if (ret)
317 return ret;
321 ret = tja11xx_get_interface_mode(phydev);
322 if (ret < 0)
323 return ret;
325 reg_val = ret & 0xffff;
326 ret = phy_modify(phydev, MII_CFG1, reg_mask, reg_val);
327 if (ret)
328 return ret;
331 ret = phy_set_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP);
332 if (ret)
333 return ret;
339 ret = phy_clear_bits(phydev, MII_CFG1, MII_CFG1_SLEEP_CONFIRM);
340 if (ret)
341 return ret;
343 ret = phy_modify(phydev, MII_CFG2, MII_CFG2_SLEEP_REQUEST_TO,
345 if (ret)
346 return ret;
348 ret = tja11xx_wakeup(phydev);
349 if (ret < 0)
350 return ret;
353 ret = phy_read(phydev, MII_INTSRC);
354 if (ret < 0)
355 return ret;
362 int ret;
367 ret = genphy_update_link(phydev);
368 if (ret)
369 return ret;
371 ret = phy_read(phydev, MII_CFG1);
372 if (ret < 0)
373 return ret;
375 if (ret & MII_CFG1_MASTER_SLAVE)
381 ret = phy_read(phydev, MII_COMMSTAT);
382 if (ret < 0)
383 return ret;
385 if (!(ret & MII_COMMSTAT_LINK_UP))
394 int ret;
396 ret = phy_read(phydev, MII_COMMSTAT);
397 if (ret < 0)
398 return ret;
400 return FIELD_GET(MII_COMMSTAT_SQI_STATE, ret);
426 int i, ret;
429 ret = phy_read(phydev, tja11xx_hw_stats[i].reg);
430 if (ret < 0)
433 data[i] = ret & tja11xx_hw_stats[i].mask;
444 int ret;
447 ret = phy_read(phydev, MII_INTSRC);
448 if (ret < 0)
449 return ret;
451 *value = !!(ret & MII_INTSRC_TEMP_ERR);
456 ret = phy_read(phydev, MII_INTSRC);
457 if (ret < 0)
458 return ret;
460 *value = !!(ret & MII_INTSRC_UV_ERR);
532 int ret;
541 ret = tja11xx_parse_dt(phydev);
542 if (ret)
543 return ret;
557 int ret;
595 ret = of_mdiobus_phy_device_register(bus, phy, child, addr);
596 if (ret) {
603 ret);
613 int ret;
622 ret = tja11xx_hwmon_register(phydev, priv);
623 if (ret)
624 return ret;
633 int ret;
638 ret = phy_read(phydev, MII_PHYSID2);
639 if (ret < 0)
640 return ret;
646 return ret ? 1 : 0;
648 return !ret;
663 int ret;
665 ret = phy_read(phydev, MII_INTSRC);
667 return (ret < 0) ? ret : 0;
720 int ret;
722 ret = phy_clear_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP);
723 if (ret)
724 return ret;
726 ret = tja11xx_wakeup(phydev);
727 if (ret < 0)
728 return ret;
730 ret = tja11xx_disable_link_control(phydev);
731 if (ret < 0)
732 return ret;
769 int ret;
771 ret = phy_read(phydev, MII_EXTSTAT);
772 if (ret < 0)
773 return ret;
776 tja11xx_cable_test_report_trans(ret));
784 int ret;
788 ret = phy_read(phydev, MII_ECTRL);
789 if (ret < 0)
790 return ret;
792 if (!(ret & MII_ECTRL_CABLE_TEST)) {
795 ret = phy_set_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP);
796 if (ret)
797 return ret;