Lines Matching defs:regmap

268 	const struct nxp_c45_regmap *regmap;
314 	return phy_data->regmap;
394 	const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(priv->phydev);
396 	nxp_c45_set_reg_field(priv->phydev, &regmap->ltc_read);
398 				   regmap->vend1_ltc_rd_nsec_0);
400 				    regmap->vend1_ltc_rd_nsec_1) << 16;
402 				  regmap->vend1_ltc_rd_sec_0);
404 				   regmap->vend1_ltc_rd_sec_1) << 16;
426 	const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(priv->phydev);
428 	phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_nsec_0,
430 	phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_nsec_1,
432 	phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_sec_0,
434 	phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_sec_1,
436 	nxp_c45_set_reg_field(priv->phydev, &regmap->ltc_write);
457 	const struct nxp_c45_regmap *regmap = data->regmap;
469 		      regmap->vend1_rate_adj_subns_0,
477 		      regmap->vend1_rate_adj_subns_1,
521 	const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(priv->phydev);
524 				      regmap->vend1_ext_trg_data_0);
526 				       regmap->vend1_ext_trg_data_1) << 16;
528 				     regmap->vend1_ext_trg_data_2);
530 				      regmap->vend1_ext_trg_data_3) << 16;
532 		      regmap->vend1_ext_trg_ctrl, RING_DONE);
552 	const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(priv->phydev);
559 			   regmap->vend1_ext_trg_ctrl);
571 			      regmap->vend1_ext_trg_ctrl, RING_DONE);
585 	const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(priv->phydev);
589 		nxp_c45_read_reg_field(phydev, &regmap->domain_number);
591 		nxp_c45_read_reg_field(phydev, &regmap->msg_type);
593 		nxp_c45_read_reg_field(phydev, &regmap->sequence_id);
595 		nxp_c45_read_reg_field(phydev, &regmap->nsec_15_0);
597 		nxp_c45_read_reg_field(phydev, &regmap->nsec_29_16) << 16;
598 	hwts->sec = nxp_c45_read_reg_field(phydev, &regmap->sec_1_0);
599 	hwts->sec |= nxp_c45_read_reg_field(phydev, &regmap->sec_4_2) << 2;
765 	const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(priv->phydev);
778 					&regmap->pps_enable);
780 					&regmap->pps_polarity);
810 						&regmap->pps_polarity);
813 					      &regmap->pps_polarity);
818 	nxp_c45_set_reg_field(priv->phydev, &regmap->pps_enable);
1058 			      data->regmap->vend1_event_msg_filt,
1063 			      data->regmap->vend1_event_msg_filt,
1072 		nxp_c45_set_reg_field(phydev, &data->regmap->irq_egr_ts_en);
1074 		nxp_c45_clear_reg_field(phydev, &data->regmap->irq_egr_ts_en);
1276 	irq = nxp_c45_read_reg_field(phydev, &data->regmap->irq_egr_ts_status);
1313 	const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(phydev);
1317 	return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, regmap->cable_test,
1324 	const struct nxp_c45_regmap *regmap = nxp_c45_get_regmap(phydev);
1328 	ret = nxp_c45_read_reg_field(phydev, &regmap->cable_test_valid);
1336 						   &regmap->cable_test_result);
1356 	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, regmap->cable_test,
1425 		      data->regmap->vend1_ptp_clk_period,
1427 	nxp_c45_clear_reg_field(phydev, &data->regmap->ltc_lock_ctrl);
1785 	.regmap = &tja1103_regmap,
1900 	.regmap = &tja1120_regmap,