Lines Matching defs:phydev
26 /* phydev->bus->mdio_lock should be locked when using this function */
27 static int phy_ts_base_write(struct phy_device *phydev, u32 regnum, u16 val)
29 struct vsc8531_private *priv = phydev->priv;
31 WARN_ON_ONCE(!mutex_is_locked(&phydev->mdio.bus->mdio_lock));
32 return __mdiobus_write(phydev->mdio.bus, priv->ts_base_addr, regnum,
36 /* phydev->bus->mdio_lock should be locked when using this function */
37 static int phy_ts_base_read(struct phy_device *phydev, u32 regnum)
39 struct vsc8531_private *priv = phydev->priv;
41 WARN_ON_ONCE(!mutex_is_locked(&phydev->mdio.bus->mdio_lock));
42 return __mdiobus_read(phydev->mdio.bus, priv->ts_base_addr, regnum);
62 static u32 vsc85xx_ts_read_csr(struct phy_device *phydev, enum ts_blk blk,
65 struct vsc8531_private *priv = phydev->priv;
66 bool base_port = phydev->mdio.addr == priv->ts_base_addr;
83 phy_lock_mdio_bus(phydev);
85 phy_ts_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_1588);
87 phy_ts_base_write(phydev, MSCC_PHY_TS_BIU_ADDR_CNTL, BIU_ADDR_EXE |
92 val = phy_ts_base_read(phydev, MSCC_PHY_TS_BIU_ADDR_CNTL);
95 val = phy_ts_base_read(phydev, MSCC_PHY_TS_CSR_DATA_MSB);
97 val |= phy_ts_base_read(phydev, MSCC_PHY_TS_CSR_DATA_LSB);
99 phy_ts_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
101 phy_unlock_mdio_bus(phydev);
106 static void vsc85xx_ts_write_csr(struct phy_device *phydev, enum ts_blk blk,
109 struct vsc8531_private *priv = phydev->priv;
110 bool base_port = phydev->mdio.addr == priv->ts_base_addr;
133 phy_lock_mdio_bus(phydev);
135 bypass = phy_ts_base_read(phydev, MSCC_PHY_BYPASS_CONTROL);
137 phy_ts_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_1588);
140 phy_ts_base_write(phydev, MSCC_PHY_TS_CSR_DATA_MSB, upper);
142 phy_ts_base_write(phydev, MSCC_PHY_TS_CSR_DATA_LSB, lower);
144 phy_ts_base_write(phydev, MSCC_PHY_TS_BIU_ADDR_CNTL, BIU_ADDR_EXE |
149 reg = phy_ts_base_read(phydev, MSCC_PHY_TS_BIU_ADDR_CNTL);
152 phy_ts_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
155 phy_ts_base_write(phydev, MSCC_PHY_BYPASS_CONTROL, bypass);
157 phy_unlock_mdio_bus(phydev);
166 static int vsc85xx_ts_fsb_init(struct phy_device *phydev)
195 vsc85xx_ts_write_csr(phydev, EGRESS, MSCC_PHY_ANA_FSB_REG(i),
199 vsc85xx_ts_write_csr(phydev, EGRESS, MSCC_PHY_ANA_FSB_REG(3),
245 static void vsc85xx_ts_set_latencies(struct phy_device *phydev)
251 if (!phydev->link)
254 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_STALL_LATENCY,
255 STALL_EGR_LATENCY(phydev->speed));
257 switch (phydev->speed) {
274 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_LOCAL_LATENCY,
277 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
280 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_TSP_CTRL,
283 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_LOCAL_LATENCY,
286 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TSP_CTRL);
288 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TSP_CTRL, val);
291 static int vsc85xx_ts_disable_flows(struct phy_device *phydev, enum ts_blk blk)
295 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_NXT_COMP, 0);
296 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_UDP_CHKSUM,
298 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP2_NXT_PROT_NXT_COMP, 0);
299 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP2_NXT_PROT_UDP_CHKSUM,
301 vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_MPLS_COMP_NXT_COMP, 0);
302 vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_ETH1_NTX_PROT, 0);
303 vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_ETH2_NTX_PROT, 0);
306 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(i),
308 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP2_FLOW_ENA(i),
310 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ENA(i),
312 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH2_FLOW_ENA(i),
314 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_MPLS_FLOW_CTRL(i),
320 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_PTP_FLOW_ENA(i), 0);
321 vsc85xx_ts_write_csr(phydev, blk,
323 vsc85xx_ts_write_csr(phydev, blk,
325 vsc85xx_ts_write_csr(phydev, blk,
327 vsc85xx_ts_write_csr(phydev, blk,
329 vsc85xx_ts_write_csr(phydev, blk,
331 vsc85xx_ts_write_csr(phydev, blk,
333 vsc85xx_ts_write_csr(phydev, blk,
335 vsc85xx_ts_write_csr(phydev, blk,
337 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_OAM_PTP_FLOW_ENA(i),
344 static int vsc85xx_ts_eth_cmp1_sig(struct phy_device *phydev)
348 val = vsc85xx_ts_read_csr(phydev, EGRESS, MSCC_PHY_ANA_ETH1_NTX_PROT);
351 vsc85xx_ts_write_csr(phydev, EGRESS, MSCC_PHY_ANA_ETH1_NTX_PROT, val);
353 val = vsc85xx_ts_read_csr(phydev, EGRESS, MSCC_PHY_ANA_FSB_CFG);
356 vsc85xx_ts_write_csr(phydev, EGRESS, MSCC_PHY_ANA_FSB_CFG, val);
440 reg = vsc85xx_ts_read_csr(ptp->phydev, PROCESSOR,
450 reg = vsc85xx_ts_read_csr(ptp->phydev, PROCESSOR,
500 reg = vsc85xx_ts_read_csr(ptp->phydev, PROCESSOR,
505 static int vsc85xx_ptp_cmp_init(struct phy_device *phydev, enum ts_blk blk)
507 struct vsc8531_private *vsc8531 = phydev->priv;
508 bool base = phydev->mdio.addr == vsc8531->ts_base_addr;
517 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_PTP_FLOW_ENA(i),
521 val = vsc85xx_ts_read_csr(phydev, blk,
524 vsc85xx_ts_write_csr(phydev, blk,
527 vsc85xx_ts_write_csr(phydev, blk,
531 vsc85xx_ts_write_csr(phydev, blk,
539 static int vsc85xx_eth_cmp1_init(struct phy_device *phydev, enum ts_blk blk)
541 struct vsc8531_private *vsc8531 = phydev->priv;
542 bool base = phydev->mdio.addr == vsc8531->ts_base_addr;
545 vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_ETH1_NXT_PROT_TAG, 0);
546 vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_ETH1_NTX_PROT_VLAN_TPID,
549 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ENA(0),
551 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_MATCH_MODE(0),
553 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ADDR_MATCH1(0), 0);
554 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ADDR_MATCH2(0), 0);
555 vsc85xx_ts_write_csr(phydev, blk,
557 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_VLAN_TAG1(0), 0);
558 vsc85xx_ts_write_csr(phydev, blk,
561 val = vsc85xx_ts_read_csr(phydev, blk,
565 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_MATCH_MODE(0),
571 static int vsc85xx_ip_cmp1_init(struct phy_device *phydev, enum ts_blk blk)
573 struct vsc8531_private *vsc8531 = phydev->priv;
574 bool base = phydev->mdio.addr == vsc8531->ts_base_addr;
577 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_MATCH2_UPPER,
580 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_MASK2_UPPER,
582 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_MATCH2_LOWER,
584 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_MASK2_LOWER, 0);
586 val = vsc85xx_ts_read_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(0));
589 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(0), val);
592 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MATCH_UPPER(0), 0);
593 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MASK_UPPER(0), 0);
594 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MATCH_UPPER_MID(0),
596 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MASK_UPPER_MID(0),
598 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MATCH_LOWER_MID(0),
600 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MASK_LOWER_MID(0),
602 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MATCH_LOWER(0), 0);
603 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_MASK_LOWER(0), 0);
605 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_PTP_IP_CHKSUM_SEL, 0);
613 struct phy_device *phydev = ptp->phydev;
614 struct vsc8531_private *priv = phydev->priv;
631 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_AUTO_ADJ,
635 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL);
637 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL, val);
647 struct phy_device *phydev = ptp->phydev;
649 (struct vsc85xx_shared_private *)phydev->shared->priv;
650 struct vsc8531_private *priv = phydev->priv;
653 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL);
655 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL, val);
663 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
668 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
672 ts->tv_nsec = vsc85xx_ts_read_csr(phydev, PROCESSOR,
684 struct phy_device *phydev = ptp->phydev;
685 struct vsc8531_private *priv = phydev->priv;
698 struct phy_device *phydev = ptp->phydev;
700 (struct vsc85xx_shared_private *)phydev->shared->priv;
701 struct vsc8531_private *priv = phydev->priv;
704 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_LOAD_SEC_MSB,
706 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_LOAD_SEC_LSB,
708 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_LOAD_NS,
711 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL);
713 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL, val);
722 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL, val);
734 struct phy_device *phydev = ptp->phydev;
735 struct vsc8531_private *priv = phydev->priv;
747 struct phy_device *phydev = ptp->phydev;
748 struct vsc8531_private *priv = phydev->priv;
773 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_OFFSET, val);
780 static int vsc85xx_eth1_next_comp(struct phy_device *phydev, enum ts_blk blk,
785 val = vsc85xx_ts_read_csr(phydev, blk, MSCC_PHY_ANA_ETH1_NTX_PROT);
788 vsc85xx_ts_write_csr(phydev, blk, MSCC_PHY_ANA_ETH1_NTX_PROT, val);
792 vsc85xx_ts_write_csr(phydev, blk,
798 static int vsc85xx_ip1_next_comp(struct phy_device *phydev, enum ts_blk blk,
801 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_NXT_COMP,
808 static int vsc85xx_ts_ptp_action_flow(struct phy_device *phydev, enum ts_blk blk, u8 flow, enum ptp_cmd cmd)
814 vsc85xx_ts_write_csr(phydev, blk,
826 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_PTP_FLOW_PTP_ACTION(flow),
841 vsc85xx_ts_write_csr(phydev, blk,
847 static int vsc85xx_ptp_conf(struct phy_device *phydev, enum ts_blk blk,
859 vsc85xx_ts_ptp_action_flow(phydev, blk, msgs[i],
863 vsc85xx_ts_ptp_action_flow(phydev, blk, msgs[i],
866 vsc85xx_ts_ptp_action_flow(phydev, blk, msgs[i],
869 val = vsc85xx_ts_read_csr(phydev, blk,
874 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_PTP_FLOW_ENA(i),
881 static int vsc85xx_eth1_conf(struct phy_device *phydev, enum ts_blk blk,
884 struct vsc8531_private *vsc8531 = phydev->priv;
893 vsc85xx_ts_write_csr(phydev, blk,
895 vsc85xx_ts_write_csr(phydev, blk,
900 vsc85xx_ts_write_csr(phydev, blk,
902 vsc85xx_ts_write_csr(phydev, blk,
906 val = vsc85xx_ts_read_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ENA(0));
910 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_ETH1_FLOW_ENA(0), val);
915 static int vsc85xx_ip1_conf(struct phy_device *phydev, enum ts_blk blk,
920 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_IP1_MODE,
928 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_IP_MATCH1,
932 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_OFFSET2,
935 val = vsc85xx_ts_read_csr(phydev, blk,
947 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_NXT_PROT_UDP_CHKSUM,
950 val = vsc85xx_ts_read_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(0));
955 vsc85xx_ts_write_csr(phydev, blk, MSCC_ANA_IP1_FLOW_ENA(0), val);
960 static int vsc85xx_ts_engine_init(struct phy_device *phydev, bool one_step)
962 struct vsc8531_private *vsc8531 = phydev->priv;
963 bool ptp_l4, base = phydev->mdio.addr == vsc8531->ts_base_addr;
969 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
974 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ANALYZER_MODE,
978 vsc85xx_eth1_next_comp(phydev, INGRESS,
980 vsc85xx_eth1_next_comp(phydev, EGRESS,
983 vsc85xx_eth1_next_comp(phydev, INGRESS,
986 vsc85xx_eth1_next_comp(phydev, EGRESS,
990 vsc85xx_ip1_next_comp(phydev, INGRESS,
992 vsc85xx_ip1_next_comp(phydev, EGRESS,
996 vsc85xx_eth1_conf(phydev, INGRESS,
998 vsc85xx_ip1_conf(phydev, INGRESS,
1000 vsc85xx_ptp_conf(phydev, INGRESS, one_step,
1003 vsc85xx_eth1_conf(phydev, EGRESS,
1005 vsc85xx_ip1_conf(phydev, EGRESS,
1007 vsc85xx_ptp_conf(phydev, EGRESS, one_step,
1018 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ANALYZER_MODE,
1024 void vsc85xx_link_change_notify(struct phy_device *phydev)
1026 struct vsc8531_private *priv = phydev->priv;
1029 vsc85xx_ts_set_latencies(phydev);
1033 static void vsc85xx_ts_reset_fifo(struct phy_device *phydev)
1037 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
1040 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TS_FIFO_CTRL,
1044 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TS_FIFO_CTRL,
1052 struct phy_device *phydev = vsc8531->ptp->phydev;
1095 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
1098 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_PREDICTOR,
1100 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
1103 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_PREDICTOR,
1107 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_IFACE_CTRL);
1113 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_IFACE_CTRL, val);
1116 vsc85xx_ts_reset_fifo(phydev);
1118 vsc85xx_ts_engine_init(phydev, one_step);
1121 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
1124 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_PREDICTOR,
1126 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
1129 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_PREDICTOR,
1235 static struct vsc8531_private *vsc8584_base_priv(struct phy_device *phydev)
1237 struct vsc8531_private *vsc8531 = phydev->priv;
1239 if (vsc8531->ts_base_addr != phydev->mdio.addr) {
1242 dev = phydev->mdio.bus->mdio_map[vsc8531->ts_base_addr];
1243 phydev = container_of(dev, struct phy_device, mdio);
1245 return phydev->priv;
1251 static bool vsc8584_is_1588_input_clk_configured(struct phy_device *phydev)
1253 struct vsc8531_private *vsc8531 = vsc8584_base_priv(phydev);
1258 static void vsc8584_set_input_clk_configured(struct phy_device *phydev)
1260 struct vsc8531_private *vsc8531 = vsc8584_base_priv(phydev);
1265 static int __vsc8584_init_ptp(struct phy_device *phydev)
1267 struct vsc8531_private *vsc8531 = phydev->priv;
1272 if (!vsc8584_is_1588_input_clk_configured(phydev)) {
1273 phy_lock_mdio_bus(phydev);
1278 phy_ts_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1280 phy_ts_base_write(phydev, 29, 0x7ae0);
1281 phy_ts_base_write(phydev, 30, 0xb71c);
1282 phy_ts_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1285 phy_unlock_mdio_bus(phydev);
1287 vsc8584_set_input_clk_configured(phydev);
1291 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
1294 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_PREDICTOR,
1296 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
1299 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_PREDICTOR,
1303 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL);
1306 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_CTRL, val);
1308 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_SEQUENCE);
1311 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_SEQUENCE, val);
1313 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_SEQ);
1318 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_SEQ, val);
1320 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_LTC_1PPS_WIDTH_ADJ,
1323 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_DELAY_FIFO,
1328 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_DELAY_FIFO,
1334 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
1344 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ACCUR_CFG_STATUS,
1347 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
1350 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ACCUR_CFG_STATUS,
1353 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
1361 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ACCUR_CFG_STATUS,
1364 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
1367 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ACCUR_CFG_STATUS,
1370 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
1373 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ACCUR_CFG_STATUS,
1377 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
1380 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_TSTAMP_FIFO_SI,
1383 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
1386 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_REWRITER_CTRL,
1388 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
1391 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_REWRITER_CTRL,
1395 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
1398 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_REWRITER_CTRL,
1400 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
1404 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_REWRITER_CTRL,
1410 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
1413 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_INGR_TSP_CTRL,
1416 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TSP_CTRL);
1418 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TSP_CTRL, val);
1420 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
1423 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_SERIAL_TOD_IFACE,
1426 vsc85xx_ts_fsb_init(phydev);
1429 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
1434 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_EGR_TS_FIFO_CTRL,
1437 vsc85xx_ts_reset_fifo(phydev);
1442 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_IFACE_CTRL, val);
1444 vsc85xx_ts_set_latencies(phydev);
1446 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_VERSION_CODE);
1448 val = vsc85xx_ts_read_csr(phydev, PROCESSOR, MSCC_PHY_PTP_IFACE_CTRL);
1450 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_IFACE_CTRL, val);
1452 vsc85xx_ts_disable_flows(phydev, EGRESS);
1453 vsc85xx_ts_disable_flows(phydev, INGRESS);
1455 val = vsc85xx_ts_read_csr(phydev, PROCESSOR,
1467 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_PTP_ANALYZER_MODE,
1475 vsc85xx_eth_cmp1_init(phydev, INGRESS);
1476 vsc85xx_ip_cmp1_init(phydev, INGRESS);
1477 vsc85xx_ptp_cmp_init(phydev, INGRESS);
1478 vsc85xx_eth_cmp1_init(phydev, EGRESS);
1479 vsc85xx_ip_cmp1_init(phydev, EGRESS);
1480 vsc85xx_ptp_cmp_init(phydev, EGRESS);
1482 vsc85xx_ts_eth_cmp1_sig(phydev);
1488 phydev->mii_ts = &vsc8531->mii_ts;
1493 &phydev->mdio.dev);
1497 void vsc8584_config_ts_intr(struct phy_device *phydev)
1499 struct vsc8531_private *priv = phydev->priv;
1502 vsc85xx_ts_write_csr(phydev, PROCESSOR, MSCC_PHY_1588_VSC85XX_INT_MASK,
1507 int vsc8584_ptp_init(struct phy_device *phydev)
1509 switch (phydev->phy_id & phydev->drv->phy_id_mask) {
1515 return __vsc8584_init_ptp(phydev);
1521 irqreturn_t vsc8584_handle_ts_interrupt(struct phy_device *phydev)
1523 struct vsc8531_private *priv = phydev->priv;
1527 rc = vsc85xx_ts_read_csr(phydev, PROCESSOR,
1530 vsc85xx_ts_write_csr(phydev, PROCESSOR,
1542 vsc85xx_ts_reset_fifo(phydev);
1549 int vsc8584_ptp_probe(struct phy_device *phydev)
1551 struct vsc8531_private *vsc8531 = phydev->priv;
1553 vsc8531->ptp = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531->ptp),
1566 vsc8531->load_save = devm_gpiod_get_optional(&phydev->mdio.dev, "load-save",
1570 phydev_err(phydev, "Can't get load-save GPIO (%ld)\n",
1575 vsc8531->ptp->phydev = phydev;
1580 int vsc8584_ptp_probe_once(struct phy_device *phydev)
1583 (struct vsc85xx_shared_private *)phydev->shared->priv;