Lines Matching refs:reg
26 .reg = MSCC_PHY_ERR_RX_CNT,
31 .reg = MSCC_PHY_ERR_FALSE_CARRIER_CNT,
36 .reg = MSCC_PHY_ERR_LINK_DISCONNECT_CNT,
41 .reg = MSCC_PHY_CU_MEDIA_CRC_VALID_CNT,
46 .reg = MSCC_PHY_EXT_PHY_CNTL_4,
55 .reg = MSCC_PHY_ERR_RX_CNT,
60 .reg = MSCC_PHY_ERR_FALSE_CARRIER_CNT,
65 .reg = MSCC_PHY_ERR_LINK_DISCONNECT_CNT,
70 .reg = MSCC_PHY_CU_MEDIA_CRC_VALID_CNT,
75 .reg = MSCC_PHY_EXT_PHY_CNTL_4,
80 .reg = MSCC_PHY_SERDES_TX_VALID_CNT,
85 .reg = MSCC_PHY_SERDES_TX_CRC_ERR_CNT,
90 .reg = MSCC_PHY_SERDES_RX_VALID_CNT,
95 .reg = MSCC_PHY_SERDES_RX_CRC_ERR_CNT,
152 priv->hw_stats[i].reg);
657 vsc85xx_tr_write(phydev, init_seq[i].reg, init_seq[i].val);
697 vsc85xx_tr_write(phydev, init_eee[i].reg, init_eee[i].val);
729 enum csr_target target, u32 reg)
756 MSCC_PHY_CSR_CNTL_19_REG_ADDR(reg) |
783 enum csr_target target, u32 reg, u32 val)
815 MSCC_PHY_CSR_CNTL_19_REG_ADDR(reg) |
909 u16 reg;
918 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
919 reg &= ~EN_PATCH_RAM_TRAP_ADDR(4);
920 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
925 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
926 reg |= EN_PATCH_RAM_TRAP_ADDR(4);
927 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
931 reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS);
932 reg &= ~MICRO_NSOFT_RESET;
933 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, reg);
939 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
940 reg &= ~EN_PATCH_RAM_TRAP_ADDR(4);
941 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
1015 u16 reg;
1021 reg = phy_base_read(phydev, MSCC_TRAP_ROM_ADDR(1));
1022 if (reg != 0x3eb7) {
1027 reg = phy_base_read(phydev, MSCC_PATCH_RAM_ADDR(1));
1028 if (reg != 0x4012) {
1033 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
1034 if (reg != EN_PATCH_RAM_TRAP_ADDR(1)) {
1039 reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS);
1041 MICRO_CLK_EN) != (reg & MSCC_DW8051_VLD_MASK)) {
1123 u16 crc, reg;
1130 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1131 reg |= SMI_BROADCAST_WR_EN;
1132 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1150 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1151 reg |= TR_CLK_DISABLE;
1152 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1157 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val);
1166 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val);
1170 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1171 reg &= ~TR_CLK_DISABLE;
1172 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1177 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1178 reg &= ~SMI_BROADCAST_WR_EN;
1179 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1377 u16 crc, reg;
1389 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1390 reg |= SMI_BROADCAST_WR_EN;
1391 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1395 reg = phy_base_read(phydev, MSCC_PHY_BYPASS_CONTROL);
1396 reg |= PARALLEL_DET_IGNORE_ADVERTISED;
1397 phy_base_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg);
1412 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1413 reg |= TR_CLK_DISABLE;
1414 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1420 reg = phy_base_read(phydev, MSCC_PHY_TR_MSB);
1421 reg &= ~0x007f;
1422 reg |= 0x0019;
1423 phy_base_write(phydev, MSCC_PHY_TR_MSB, reg);
1428 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val);
1437 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val);
1441 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1442 reg &= ~TR_CLK_DISABLE;
1443 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1448 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1449 reg &= ~SMI_BROADCAST_WR_EN;
1450 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1492 reg = MSCC_ROM_TRAP_SERDES_6G_CFG; /* ROM address to trap, for patch vector 0 */
1493 ret = phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), reg);
1497 reg = MSCC_RAM_TRAP_SERDES_6G_CFG; /* RAM address to jump to, when patch vector 0 enabled */
1498 ret = phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), reg);
1502 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
1503 reg |= PATCH_VEC_ZERO_EN; /* bit 8, enable patch vector 0 */
1504 ret = phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
1560 /* The coma mode (pin or reg) provides an optional feature that
1870 static int __phy_write_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb,
1877 ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET, reg,
1885 val = vsc85xx_csr_read(phydev, PHY_MCB_TARGET, reg);
1899 int phy_update_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb)
1901 return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_READ);
1905 int phy_commit_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb)
1907 return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_WRITE);
1994 u16 reg;
2006 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
2007 reg |= SMI_BROADCAST_WR_EN;
2008 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
2012 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
2013 reg |= BIT(15);
2014 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
2019 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val);
2023 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
2024 reg &= ~BIT(15);
2025 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
2029 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
2030 reg &= ~SMI_BROADCAST_WR_EN;
2031 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
2045 reg = MSCC_ROM_TRAP_SERDES_6G_CFG;
2046 ret = phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), reg);
2050 reg = MSCC_RAM_TRAP_SERDES_6G_CFG;
2051 ret = phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), reg);
2054 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
2055 reg |= PATCH_VEC_ZERO_EN; /* bit 8, enable patch vector 0 */
2056 ret = phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);