Lines Matching defs:val
404 u32 regnum, u16 val)
407 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
481 static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
489 if (val)
497 static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
519 temp |= val << shift;
690 u16 val;
694 val = KSZ8081_CTRL2_DISABLE_AUTO_MDIX;
697 val = KSZ8081_CTRL2_DISABLE_AUTO_MDIX |
701 val = 0;
711 KSZ8081_CTRL2_HP_MDIX | val);
930 int val[4] = {-1, -2, -3, -4};
938 if (!of_property_read_u32(of_node, field[i], val + i))
953 if (val[i] != -(i + 1)) {
957 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
1159 int val[4] = {-(1 + KSZ9131_OFFSET), -(2 + KSZ9131_OFFSET),
1181 val[i] = skewval + KSZ9131_OFFSET;
1195 if (val[i] != -(i + 1 + KSZ9131_OFFSET)) {
1199 (((val[i] / KSZ9131_STEP) & maxval)
1362 u16 val;
1366 val = MII_KSZ9131_AUTO_MDIX_SWAP_OFF |
1370 val = MII_KSZ9131_AUTO_MDIX_SWAP_OFF;
1373 val = 0;
1381 MII_KSZ9131_AUTO_MDI_SET, val);
1589 int val, ret;
1591 ret = phy_read_poll_timeout(phydev, KSZ9x31_LMD, val,
1592 !(val & KSZ9x31_LMD_VCT_EN),
1612 int ret, val;
1630 val = phy_read(phydev, KSZ9x31_LMD);
1631 if (val < 0)
1632 return val;
1634 if (ksz9x31_cable_test_failed(val))
1639 ksz9x31_cable_test_result_trans(val));
1643 if (!ksz9x31_cable_test_fault_length_valid(val))
1648 ksz9x31_cable_test_fault_length(phydev, val));
1705 u16 val;
1709 val = KSZ886X_BMCR_DISABLE_AUTO_MDIX;
1718 val = KSZ886X_BMCR_DISABLE_AUTO_MDIX | KSZ886X_BMCR_FORCE_MDI;
1721 val = 0;
1730 KSZ886X_BMCR_HP_MDIX | val);
1792 u16 val;
1847 err = phy_write_mmd(phydev, errata->dev_addr, errata->reg_addr, errata->val);
1884 int val;
1887 val = phy_read(phydev, stat.reg);
1888 if (val < 0) {
1891 val = val & ((1 << stat.bits) - 1);
1892 priv->stats[i] += val;
2098 int val, ret;
2100 ret = phy_read_poll_timeout(phydev, type->cable_diag_reg, val,
2101 !(val & KSZ8081_LMD_ENABLE_TEST),
2116 int val;
2118 val = KSZ8081_LMD_ENABLE_TEST;
2119 val = val | (pair << LAN8814_PAIR_BIT_SHIFT);
2121 ret = phy_write(phydev, LAN8814_CABLE_DIAG, val);
2129 val = phy_read(phydev, LAN8814_CABLE_DIAG);
2130 if (val < 0)
2131 return val;
2133 if (ksz886x_cable_test_failed(val, LAN8814_CABLE_DIAG_STAT_MASK))
2137 ksz886x_cable_test_result_trans(val,
2143 if (!ksz886x_cable_test_fault_length_valid(val, LAN8814_CABLE_DIAG_STAT_MASK))
2146 fault_length = ksz886x_cable_test_fault_length(phydev, val,
2158 int ret, val, mdix;
2194 val = phy_read(phydev, KSZ8081_LMD);
2195 if (val < 0)
2196 return val;
2198 if (ksz886x_cable_test_failed(val, KSZ8081_LMD_STAT_MASK))
2202 ksz886x_cable_test_result_trans(val, KSZ8081_LMD_STAT_MASK));
2206 if (!ksz886x_cable_test_fault_length_valid(val, KSZ8081_LMD_STAT_MASK))
2209 fault_length = ksz886x_cable_test_fault_length(phydev, val, KSZ8081_LMD_DELTA_TIME_MASK);
2285 u16 val)
2293 val = __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, val);
2294 if (val != 0)
2296 val);
2298 return val;
2303 u16 val = 0;
2306 val = PTP_TSU_INT_EN_PTP_TX_TS_EN_ |
2311 return lanphy_write_page_reg(phydev, 5, PTP_TSU_INT_EN, val);
2963 int val;
2966 val = lanphy_read_page_reg(phydev, 2, LAN8804_ALIGN_SWAP);
2967 val &= ~LAN8804_ALIGN_TX_A_B_SWAP_MASK;
2968 val |= LAN8804_ALIGN_TX_A_B_SWAP;
2969 lanphy_write_page_reg(phydev, 2, LAN8804_ALIGN_SWAP, val);
3201 static void lan8814_setup_led(struct phy_device *phydev, int val)
3207 if (val)
3218 int val;
3221 val = lanphy_read_page_reg(phydev, 4, LAN8814_QSGMII_SOFT_RESET);
3222 val |= LAN8814_QSGMII_SOFT_RESET_BIT;
3223 lanphy_write_page_reg(phydev, 4, LAN8814_QSGMII_SOFT_RESET, val);
3226 val = lanphy_read_page_reg(phydev, 5, LAN8814_QSGMII_PCS1G_ANEG_CONFIG);
3227 val &= ~LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA;
3228 lanphy_write_page_reg(phydev, 5, LAN8814_QSGMII_PCS1G_ANEG_CONFIG, val);
3231 val = lanphy_read_page_reg(phydev, 2, LAN8814_ALIGN_SWAP);
3232 val &= ~LAN8814_ALIGN_TX_A_B_SWAP_MASK;
3233 val |= LAN8814_ALIGN_TX_A_B_SWAP;
3234 lanphy_write_page_reg(phydev, 2, LAN8814_ALIGN_SWAP, val);