Lines Matching defs:phydev

289 	struct phy_device *phydev;
311 struct phy_device *phydev;
403 static int kszphy_extended_write(struct phy_device *phydev,
406 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
407 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
410 static int kszphy_extended_read(struct phy_device *phydev,
413 phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
414 return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
417 static int kszphy_ack_interrupt(struct phy_device *phydev)
422 rc = phy_read(phydev, MII_KSZPHY_INTCS);
427 static int kszphy_config_intr(struct phy_device *phydev)
429 const struct kszphy_type *type = phydev->drv->driver_data;
439 temp = phy_read(phydev, MII_KSZPHY_CTRL);
443 phy_write(phydev, MII_KSZPHY_CTRL, temp);
446 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
447 err = kszphy_ack_interrupt(phydev);
451 err = phy_write(phydev, MII_KSZPHY_INTCS, KSZPHY_INTCS_ALL);
453 err = phy_write(phydev, MII_KSZPHY_INTCS, 0);
457 err = kszphy_ack_interrupt(phydev);
463 static irqreturn_t kszphy_handle_interrupt(struct phy_device *phydev)
467 irq_status = phy_read(phydev, MII_KSZPHY_INTCS);
469 phy_error(phydev);
476 phy_trigger_machine(phydev);
481 static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
485 ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
494 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
497 static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
512 temp = phy_read(phydev, reg);
520 rc = phy_write(phydev, reg, temp);
523 phydev_err(phydev, "failed to set led mode\n");
531 static int kszphy_broadcast_disable(struct phy_device *phydev)
535 ret = phy_read(phydev, MII_KSZPHY_OMSO);
539 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
542 phydev_err(phydev, "failed to disable broadcast address\n");
547 static int kszphy_nand_tree_disable(struct phy_device *phydev)
551 ret = phy_read(phydev, MII_KSZPHY_OMSO);
558 ret = phy_write(phydev, MII_KSZPHY_OMSO,
562 phydev_err(phydev, "failed to disable NAND tree mode\n");
568 static int kszphy_config_reset(struct phy_device *phydev)
570 struct kszphy_priv *priv = phydev->priv;
574 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
576 phydev_err(phydev,
583 kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode);
588 static int kszphy_config_init(struct phy_device *phydev)
590 struct kszphy_priv *priv = phydev->priv;
599 kszphy_broadcast_disable(phydev);
602 kszphy_nand_tree_disable(phydev);
604 return kszphy_config_reset(phydev);
607 static int ksz8041_fiber_mode(struct phy_device *phydev)
609 struct device_node *of_node = phydev->mdio.dev.of_node;
614 static int ksz8041_config_init(struct phy_device *phydev)
619 if (ksz8041_fiber_mode(phydev)) {
620 phydev->dev_flags |= MICREL_PHY_FXEN;
624 linkmode_and(phydev->supported, phydev->supported, mask);
626 phydev->supported);
627 linkmode_and(phydev->advertising, phydev->advertising, mask);
629 phydev->advertising);
630 phydev->autoneg = AUTONEG_DISABLE;
633 return kszphy_config_init(phydev);
636 static int ksz8041_config_aneg(struct phy_device *phydev)
639 if (phydev->dev_flags & MICREL_PHY_FXEN) {
640 phydev->speed = SPEED_100;
644 return genphy_config_aneg(phydev);
647 static int ksz8051_ksz8795_match_phy_device(struct phy_device *phydev,
652 if (!phy_id_compare(phydev->phy_id, PHY_ID_KSZ8051, MICREL_PHY_ID_MASK))
655 ret = phy_read(phydev, MII_BMSR);
671 static int ksz8051_match_phy_device(struct phy_device *phydev)
673 return ksz8051_ksz8795_match_phy_device(phydev, true);
676 static int ksz8081_config_init(struct phy_device *phydev)
683 phy_clear_bits(phydev, MII_KSZPHY_OMSO, KSZPHY_OMSO_FACTORY_TEST);
685 return kszphy_config_init(phydev);
688 static int ksz8081_config_mdix(struct phy_device *phydev, u8 ctrl)
707 return phy_modify(phydev, MII_KSZPHY_CTRL_2,
714 static int ksz8081_config_aneg(struct phy_device *phydev)
718 ret = genphy_config_aneg(phydev);
726 return ksz8081_config_mdix(phydev, phydev->mdix_ctrl);
729 static int ksz8081_mdix_update(struct phy_device *phydev)
733 ret = phy_read(phydev, MII_KSZPHY_CTRL_2);
739 phydev->mdix_ctrl = ETH_TP_MDI_X;
741 phydev->mdix_ctrl = ETH_TP_MDI;
743 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
746 ret = phy_read(phydev, MII_KSZPHY_CTRL_1);
751 phydev->mdix = ETH_TP_MDI;
753 phydev->mdix = ETH_TP_MDI_X;
758 static int ksz8081_read_status(struct phy_device *phydev)
762 ret = ksz8081_mdix_update(phydev);
766 return genphy_read_status(phydev);
769 static int ksz8061_config_init(struct phy_device *phydev)
773 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A);
777 return kszphy_config_init(phydev);
780 static int ksz8795_match_phy_device(struct phy_device *phydev)
782 return ksz8051_ksz8795_match_phy_device(phydev, false);
785 static int ksz9021_load_values_from_of(struct phy_device *phydev,
814 newval = kszphy_extended_read(phydev, reg);
830 return kszphy_extended_write(phydev, reg, newval);
833 static int ksz9021_config_init(struct phy_device *phydev)
842 dev_walker = &phydev->mdio.dev;
850 ksz9021_load_values_from_of(phydev, of_node,
854 ksz9021_load_values_from_of(phydev, of_node,
858 ksz9021_load_values_from_of(phydev, of_node,
924 static int ksz9031_of_load_skew_values(struct phy_device *phydev,
947 newval = phy_read_mmd(phydev, 2, reg);
961 return phy_write_mmd(phydev, 2, reg, newval);
965 static int ksz9031_center_flp_timing(struct phy_device *phydev)
969 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_HI,
974 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_LO,
979 return genphy_restart_aneg(phydev);
983 static int ksz9031_enable_edpd(struct phy_device *phydev)
987 reg = phy_read_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD);
990 return phy_write_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD,
994 static int ksz9031_config_rgmii_delay(struct phy_device *phydev)
999 switch (phydev->interface) {
1028 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_CONTROL_PAD_SKEW,
1034 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_RX_DATA_PAD_SKEW,
1042 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_TX_DATA_PAD_SKEW,
1050 return phy_write_mmd(phydev, 2, MII_KSZ9031RN_CLK_PAD_SKEW,
1055 static int ksz9031_config_init(struct phy_device *phydev)
1071 result = ksz9031_enable_edpd(phydev);
1079 dev_walker = &phydev->mdio.dev;
1088 if (phy_interface_is_rgmii(phydev)) {
1089 result = ksz9031_config_rgmii_delay(phydev);
1094 ksz9031_of_load_skew_values(phydev, of_node,
1098 ksz9031_of_load_skew_values(phydev, of_node,
1102 ksz9031_of_load_skew_values(phydev, of_node,
1106 ksz9031_of_load_skew_values(phydev, of_node,
1110 if (update && !phy_interface_is_rgmii(phydev))
1111 phydev_warn(phydev,
1130 result = phy_read(phydev, MII_CTRL1000);
1136 result = phy_write(phydev, MII_CTRL1000, result);
1142 return ksz9031_center_flp_timing(phydev);
1145 phydev_err(phydev, "failed to force the phy to master mode\n");
1154 static int ksz9131_of_load_skew_values(struct phy_device *phydev,
1189 newval = phy_read_mmd(phydev, 2, reg);
1203 return phy_write_mmd(phydev, 2, reg, newval);
1211 static int ksz9131_config_rgmii_delay(struct phy_device *phydev)
1213 const struct kszphy_type *type = phydev->drv->driver_data;
1217 switch (phydev->interface) {
1238 ret = phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
1244 return phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
1255 static int ksz9131_led_errata(struct phy_device *phydev)
1259 reg = phy_read_mmd(phydev, 2, 0);
1266 return phy_set_bits(phydev, 0x1e, BIT(9));
1269 static int ksz9131_config_init(struct phy_device *phydev)
1285 dev_walker = &phydev->mdio.dev;
1294 if (phy_interface_is_rgmii(phydev)) {
1295 ret = ksz9131_config_rgmii_delay(phydev);
1300 ret = ksz9131_of_load_skew_values(phydev, of_node,
1306 ret = ksz9131_of_load_skew_values(phydev, of_node,
1312 ret = ksz9131_of_load_skew_values(phydev, of_node,
1318 ret = ksz9131_of_load_skew_values(phydev, of_node,
1324 ret = ksz9131_led_errata(phydev);
1335 static int ksz9131_mdix_update(struct phy_device *phydev)
1339 ret = phy_read(phydev, MII_KSZ9131_AUTO_MDIX);
1345 phydev->mdix_ctrl = ETH_TP_MDI;
1347 phydev->mdix_ctrl = ETH_TP_MDI_X;
1349 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1353 phydev->mdix = ETH_TP_MDI;
1355 phydev->mdix = ETH_TP_MDI_X;
1360 static int ksz9131_config_mdix(struct phy_device *phydev, u8 ctrl)
1379 return phy_modify(phydev, MII_KSZ9131_AUTO_MDIX,
1384 static int ksz9131_read_status(struct phy_device *phydev)
1388 ret = ksz9131_mdix_update(phydev);
1392 return genphy_read_status(phydev);
1395 static int ksz9131_config_aneg(struct phy_device *phydev)
1399 ret = ksz9131_config_mdix(phydev, phydev->mdix_ctrl);
1403 return genphy_config_aneg(phydev);
1406 static int ksz9477_get_features(struct phy_device *phydev)
1410 ret = genphy_read_abilities(phydev);
1420 linkmode_and(phydev->supported_eee, phydev->supported,
1429 static int ksz8873mll_read_status(struct phy_device *phydev)
1434 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
1436 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
1439 phydev->duplex = DUPLEX_HALF;
1441 phydev->duplex = DUPLEX_FULL;
1444 phydev->speed = SPEED_10;
1446 phydev->speed = SPEED_100;
1448 phydev->link = 1;
1449 phydev->pause = phydev->asym_pause = 0;
1454 static int ksz9031_get_features(struct phy_device *phydev)
1458 ret = genphy_read_abilities(phydev);
1471 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported);
1476 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported);
1481 static int ksz9031_read_status(struct phy_device *phydev)
1486 err = genphy_read_status(phydev);
1493 regval = phy_read(phydev, MII_STAT1000);
1495 phy_init_hw(phydev);
1496 phydev->link = 0;
1497 if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev))
1498 phydev->drv->config_intr(phydev);
1499 return genphy_config_aneg(phydev);
1505 static int ksz9x31_cable_test_start(struct phy_device *phydev)
1507 struct kszphy_priv *priv = phydev->priv;
1515 ret = phy_modify(phydev, MII_BMCR,
1527 ret = phy_read(phydev, MII_CTRL1000);
1536 return phy_write(phydev, MII_CTRL1000, ret);
1573 static int ksz9x31_cable_test_fault_length(struct phy_device *phydev, u16 stat)
1581 if (phydev_id_compare(phydev, PHY_ID_KSZ9131))
1587 static int ksz9x31_cable_test_wait_for_completion(struct phy_device *phydev)
1591 ret = phy_read_poll_timeout(phydev, KSZ9x31_LMD, val,
1610 static int ksz9x31_cable_test_one_pair(struct phy_device *phydev, int pair)
1621 ret = phy_write(phydev, KSZ9x31_LMD,
1626 ret = ksz9x31_cable_test_wait_for_completion(phydev);
1630 val = phy_read(phydev, KSZ9x31_LMD);
1637 ret = ethnl_cable_test_result(phydev,
1646 return ethnl_cable_test_fault_length(phydev,
1648 ksz9x31_cable_test_fault_length(phydev, val));
1651 static int ksz9x31_cable_test_get_status(struct phy_device *phydev,
1654 struct kszphy_priv *priv = phydev->priv;
1664 ret = ksz9x31_cable_test_one_pair(phydev, pair);
1681 ret = ethnl_cable_test_result(phydev,
1689 rv = phy_modify(phydev, MII_CTRL1000,
1698 static int ksz8873mll_config_aneg(struct phy_device *phydev)
1703 static int ksz886x_config_mdix(struct phy_device *phydev, u8 ctrl)
1727 return phy_modify(phydev, MII_BMCR,
1733 static int ksz886x_config_aneg(struct phy_device *phydev)
1737 ret = genphy_config_aneg(phydev);
1745 return ksz886x_config_mdix(phydev, phydev->mdix_ctrl);
1748 static int ksz886x_mdix_update(struct phy_device *phydev)
1752 ret = phy_read(phydev, MII_BMCR);
1758 phydev->mdix_ctrl = ETH_TP_MDI_X;
1760 phydev->mdix_ctrl = ETH_TP_MDI;
1762 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1765 ret = phy_read(phydev, MII_KSZPHY_CTRL);
1771 phydev->mdix = ETH_TP_MDI_X;
1773 phydev->mdix = ETH_TP_MDI;
1778 static int ksz886x_read_status(struct phy_device *phydev)
1782 ret = ksz886x_mdix_update(phydev);
1786 return genphy_read_status(phydev);
1824 static int ksz9477_config_init(struct phy_device *phydev)
1840 err = phy_write(phydev, MII_BMCR, BMCR_SPEED100 | BMCR_FULLDPLX);
1847 err = phy_write_mmd(phydev, errata->dev_addr, errata->reg_addr, errata->val);
1855 if (phydev->dev_flags & MICREL_NO_EEE)
1856 phydev->eee_broken_modes = -1;
1858 err = genphy_restart_aneg(phydev);
1862 return kszphy_config_init(phydev);
1865 static int kszphy_get_sset_count(struct phy_device *phydev)
1870 static void kszphy_get_strings(struct phy_device *phydev, u8 *data)
1880 static u64 kszphy_get_stat(struct phy_device *phydev, int i)
1883 struct kszphy_priv *priv = phydev->priv;
1887 val = phy_read(phydev, stat.reg);
1899 static void kszphy_get_stats(struct phy_device *phydev,
1905 data[i] = kszphy_get_stat(phydev, i);
1908 static int kszphy_suspend(struct phy_device *phydev)
1911 if (phy_interrupt_is_valid(phydev)) {
1912 phydev->interrupts = PHY_INTERRUPT_DISABLED;
1913 if (phydev->drv->config_intr)
1914 phydev->drv->config_intr(phydev);
1917 return genphy_suspend(phydev);
1920 static void kszphy_parse_led_mode(struct phy_device *phydev)
1922 const struct kszphy_type *type = phydev->drv->driver_data;
1923 const struct device_node *np = phydev->mdio.dev.of_node;
1924 struct kszphy_priv *priv = phydev->priv;
1935 phydev_err(phydev, "invalid led mode: 0x%02x\n",
1944 static int kszphy_resume(struct phy_device *phydev)
1948 genphy_resume(phydev);
1956 ret = kszphy_config_reset(phydev);
1961 if (phy_interrupt_is_valid(phydev)) {
1962 phydev->interrupts = PHY_INTERRUPT_ENABLED;
1963 if (phydev->drv->config_intr)
1964 phydev->drv->config_intr(phydev);
1970 static int kszphy_probe(struct phy_device *phydev)
1972 const struct kszphy_type *type = phydev->drv->driver_data;
1973 const struct device_node *np = phydev->mdio.dev.of_node;
1977 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
1981 phydev->priv = priv;
1985 kszphy_parse_led_mode(phydev);
1987 clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref");
2003 phydev_err(phydev, "Clock rate out of range: %ld\n",
2009 if (ksz8041_fiber_mode(phydev))
2010 phydev->port = PORT_FIBRE;
2013 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
2021 static int lan8814_cable_test_start(struct phy_device *phydev)
2028 return phy_modify(phydev, MII_BMCR, BMCR_ANENABLE | BMCR_SPEED100,
2032 static int ksz886x_cable_test_start(struct phy_device *phydev)
2034 if (phydev->dev_flags & MICREL_KSZ8_P1_ERRATA)
2042 return phy_clear_bits(phydev, MII_BMCR, BMCR_ANENABLE | BMCR_SPEED100);
2078 static __always_inline int ksz886x_cable_test_fault_length(struct phy_device *phydev,
2089 if (phydev_id_compare(phydev, PHY_ID_LAN8814))
2095 static int ksz886x_cable_test_wait_for_completion(struct phy_device *phydev)
2097 const struct kszphy_type *type = phydev->drv->driver_data;
2100 ret = phy_read_poll_timeout(phydev, type->cable_diag_reg, val,
2107 static int lan8814_cable_test_one_pair(struct phy_device *phydev, int pair)
2121 ret = phy_write(phydev, LAN8814_CABLE_DIAG, val);
2125 ret = ksz886x_cable_test_wait_for_completion(phydev);
2129 val = phy_read(phydev, LAN8814_CABLE_DIAG);
2136 ret = ethnl_cable_test_result(phydev, ethtool_pair[pair],
2146 fault_length = ksz886x_cable_test_fault_length(phydev, val,
2149 return ethnl_cable_test_fault_length(phydev, ethtool_pair[pair], fault_length);
2152 static int ksz886x_cable_test_one_pair(struct phy_device *phydev, int pair)
2169 switch (phydev->phy_id & MICREL_PHY_ID_MASK) {
2171 ret = ksz8081_config_mdix(phydev, mdix);
2174 ret = ksz886x_config_mdix(phydev, mdix);
2186 ret = phy_write(phydev, KSZ8081_LMD, KSZ8081_LMD_ENABLE_TEST);
2190 ret = ksz886x_cable_test_wait_for_completion(phydev);
2194 val = phy_read(phydev, KSZ8081_LMD);
2201 ret = ethnl_cable_test_result(phydev, ethtool_pair[pair],
2209 fault_length = ksz886x_cable_test_fault_length(phydev, val, KSZ8081_LMD_DELTA_TIME_MASK);
2211 return ethnl_cable_test_fault_length(phydev, ethtool_pair[pair], fault_length);
2214 static int ksz886x_cable_test_get_status(struct phy_device *phydev,
2217 const struct kszphy_type *type = phydev->drv->driver_data;
2229 ret = lan8814_cable_test_one_pair(phydev, pair);
2231 ret = ksz886x_cable_test_one_pair(phydev, pair);
2269 static int lanphy_read_page_reg(struct phy_device *phydev, int page, u32 addr)
2273 phy_lock_mdio_bus(phydev);
2274 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, page);
2275 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, addr);
2276 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL,
2278 data = __phy_read(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA);
2279 phy_unlock_mdio_bus(phydev);
2284 static int lanphy_write_page_reg(struct phy_device *phydev, int page, u16 addr,
2287 phy_lock_mdio_bus(phydev);
2288 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, page);
2289 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, addr);
2290 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL,
2293 val = __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, val);
2295 phydev_err(phydev, "Error: phy_write has returned error %d\n",
2297 phy_unlock_mdio_bus(phydev);
2301 static int lan8814_config_ts_intr(struct phy_device *phydev, bool enable)
2311 return lanphy_write_page_reg(phydev, 5, PTP_TSU_INT_EN, val);
2314 static void lan8814_ptp_rx_ts_get(struct phy_device *phydev,
2317 *seconds = lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_SEC_HI);
2319 lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_SEC_LO);
2321 *nano_seconds = lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_NS_HI);
2323 lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_NS_LO);
2325 *seq_id = lanphy_read_page_reg(phydev, 5, PTP_RX_MSG_HEADER2);
2328 static void lan8814_ptp_tx_ts_get(struct phy_device *phydev,
2331 *seconds = lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_SEC_HI);
2333 lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_SEC_LO);
2335 *nano_seconds = lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_NS_HI);
2337 lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_NS_LO);
2339 *seq_id = lanphy_read_page_reg(phydev, 5, PTP_TX_MSG_HEADER2);
2345 struct phy_device *phydev = ptp_priv->phydev;
2346 struct lan8814_shared_priv *shared = phydev->shared->priv;
2369 static void lan8814_flush_fifo(struct phy_device *phydev, bool egress)
2374 lanphy_read_page_reg(phydev, 5,
2378 lanphy_read_page_reg(phydev, 5, PTP_TSU_INT_STS);
2385 struct phy_device *phydev = ptp_priv->phydev;
2386 struct lan8814_shared_priv *shared = phydev->shared->priv;
2432 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_RX_PARSE_CONFIG, rxcfg);
2433 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_PARSE_CONFIG, txcfg);
2437 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_RX_TIMESTAMP_EN, pkt_ts_enable);
2438 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_TIMESTAMP_EN, pkt_ts_enable);
2441 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_MOD,
2445 lan8814_config_ts_intr(ptp_priv->phydev, true);
2447 lan8814_config_ts_intr(ptp_priv->phydev, false);
2456 lanphy_write_page_reg(ptp_priv->phydev, 4, PTP_CMD_CTL,
2459 lanphy_write_page_reg(ptp_priv->phydev, 4, PTP_CMD_CTL,
2471 lan8814_flush_fifo(ptp_priv->phydev, false);
2472 lan8814_flush_fifo(ptp_priv->phydev, true);
2569 static void lan8814_ptp_clock_set(struct phy_device *phydev,
2579 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_SEC_LO, sec_low);
2580 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_SEC_MID, sec_high);
2581 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_NS_LO, nsec_low);
2582 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_NS_HI, nsec_high);
2584 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_CLOCK_LOAD_);
2587 static void lan8814_ptp_clock_get(struct phy_device *phydev,
2590 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_CLOCK_READ_);
2592 *seconds = lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_SEC_MID);
2594 lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_SEC_LO);
2596 *nano_seconds = lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_NS_HI);
2598 lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_NS_LO);
2606 struct phy_device *phydev = shared->phydev;
2611 lan8814_ptp_clock_get(phydev, &seconds, &nano_seconds);
2624 struct phy_device *phydev = shared->phydev;
2627 lan8814_ptp_clock_set(phydev, ts->tv_sec, ts->tv_nsec);
2633 static void lan8814_ptp_clock_step(struct phy_device *phydev,
2645 lan8814_ptp_clock_get(phydev, &unsigned_seconds, &nano_seconds);
2653 lan8814_ptp_clock_set(phydev, unsigned_seconds, nano_seconds);
2659 lan8814_ptp_clock_get(phydev, &unsigned_seconds, &nano_seconds);
2668 lan8814_ptp_clock_set(phydev, unsigned_seconds,
2716 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
2718 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
2732 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
2734 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
2738 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL,
2748 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
2750 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
2753 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL,
2762 struct phy_device *phydev = shared->phydev;
2765 lan8814_ptp_clock_step(phydev, delta);
2775 struct phy_device *phydev = shared->phydev;
2795 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_RATE_ADJ_HI, kszphy_rate_adj_hi);
2796 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_RATE_ADJ_LO, kszphy_rate_adj_lo);
2844 struct phy_device *phydev = ptp_priv->phydev;
2848 lan8814_ptp_tx_ts_get(phydev, &seconds, &nsec, &seq_id);
2854 struct phy_device *phydev = ptp_priv->phydev;
2863 reg = lanphy_read_page_reg(phydev, 5, PTP_CAP_INFO);
2919 struct phy_device *phydev = ptp_priv->phydev;
2928 lan8814_ptp_rx_ts_get(phydev, &rx_ts->seconds, &rx_ts->nsec,
2935 reg = lanphy_read_page_reg(phydev, 5, PTP_CAP_INFO);
2939 static void lan8814_handle_ptp_interrupt(struct phy_device *phydev, u16 status)
2941 struct kszphy_priv *priv = phydev->priv;
2951 lan8814_flush_fifo(phydev, true);
2956 lan8814_flush_fifo(phydev, false);
2961 static int lan8804_config_init(struct phy_device *phydev)
2966 val = lanphy_read_page_reg(phydev, 2, LAN8804_ALIGN_SWAP);
2969 lanphy_write_page_reg(phydev, 2, LAN8804_ALIGN_SWAP, val);
2974 lanphy_write_page_reg(phydev, 31, LAN8814_CLOCK_MANAGEMENT, 0x27e);
2975 lanphy_read_page_reg(phydev, 1, LAN8814_LINK_QUALITY);
2980 static irqreturn_t lan8804_handle_interrupt(struct phy_device *phydev)
2984 status = phy_read(phydev, LAN8814_INTS);
2986 phy_error(phydev);
2991 phy_trigger_machine(phydev);
3001 static int lan8804_config_intr(struct phy_device *phydev)
3010 phy_write(phydev, LAN8804_CONTROL, LAN8804_CONTROL_INTR_POLARITY);
3016 phy_write(phydev, LAN8804_OUTPUT_CONTROL,
3019 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
3020 err = phy_read(phydev, LAN8814_INTS);
3024 err = phy_write(phydev, LAN8814_INTC, LAN8814_INT_LINK);
3028 err = phy_write(phydev, LAN8814_INTC, 0);
3032 err = phy_read(phydev, LAN8814_INTS);
3040 static irqreturn_t lan8814_handle_interrupt(struct phy_device *phydev)
3045 irq_status = phy_read(phydev, LAN8814_INTS);
3047 phy_error(phydev);
3052 phy_trigger_machine(phydev);
3057 irq_status = lanphy_read_page_reg(phydev, 5, PTP_TSU_INT_STS);
3061 lan8814_handle_ptp_interrupt(phydev, irq_status);
3068 static int lan8814_ack_interrupt(struct phy_device *phydev)
3073 rc = phy_read(phydev, LAN8814_INTS);
3078 static int lan8814_config_intr(struct phy_device *phydev)
3082 lanphy_write_page_reg(phydev, 4, LAN8814_INTR_CTRL_REG,
3087 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
3088 err = lan8814_ack_interrupt(phydev);
3092 err = phy_write(phydev, LAN8814_INTC, LAN8814_INT_LINK);
3094 err = phy_write(phydev, LAN8814_INTC, 0);
3098 err = lan8814_ack_interrupt(phydev);
3104 static void lan8814_ptp_init(struct phy_device *phydev)
3106 struct kszphy_priv *priv = phydev->priv;
3114 lanphy_write_page_reg(phydev, 5, TSU_HARD_RESET, TSU_HARD_RESET_);
3116 temp = lanphy_read_page_reg(phydev, 5, PTP_TX_MOD);
3118 lanphy_write_page_reg(phydev, 5, PTP_TX_MOD, temp);
3120 temp = lanphy_read_page_reg(phydev, 5, PTP_RX_MOD);
3122 lanphy_write_page_reg(phydev, 5, PTP_RX_MOD, temp);
3124 lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_CONFIG, 0);
3125 lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_CONFIG, 0);
3128 lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_L2_ADDR_EN, 0);
3129 lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_L2_ADDR_EN, 0);
3130 lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_IP_ADDR_EN, 0);
3131 lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_IP_ADDR_EN, 0);
3134 lanphy_write_page_reg(phydev, 5, PTP_RX_VERSION,
3136 lanphy_write_page_reg(phydev, 5, PTP_TX_VERSION,
3144 ptp_priv->phydev = phydev;
3151 phydev->mii_ts = &ptp_priv->mii_ts;
3154 static int lan8814_ptp_probe_once(struct phy_device *phydev)
3156 struct lan8814_shared_priv *shared = phydev->shared->priv;
3162 snprintf(shared->ptp_clock_info.name, 30, "%s", phydev->drv->name);
3176 &phydev->mdio.dev);
3178 phydev_err(phydev, "ptp_clock_register failed %lu\n",
3187 phydev_dbg(phydev, "successfully registered ptp clock\n");
3189 shared->phydev = phydev;
3194 lanphy_write_page_reg(phydev, 4, LTC_HARD_RESET, LTC_HARD_RESET_);
3195 lanphy_write_page_reg(phydev, 4, PTP_OPERATING_MODE,
3201 static void lan8814_setup_led(struct phy_device *phydev, int val)
3205 temp = lanphy_read_page_reg(phydev, 5, LAN8814_LED_CTRL_1);
3212 lanphy_write_page_reg(phydev, 5, LAN8814_LED_CTRL_1, temp);
3215 static int lan8814_config_init(struct phy_device *phydev)
3217 struct kszphy_priv *lan8814 = phydev->priv;
3221 val = lanphy_read_page_reg(phydev, 4, LAN8814_QSGMII_SOFT_RESET);
3223 lanphy_write_page_reg(phydev, 4, LAN8814_QSGMII_SOFT_RESET, val);
3226 val = lanphy_read_page_reg(phydev, 5, LAN8814_QSGMII_PCS1G_ANEG_CONFIG);
3228 lanphy_write_page_reg(phydev, 5, LAN8814_QSGMII_PCS1G_ANEG_CONFIG, val);
3231 val = lanphy_read_page_reg(phydev, 2, LAN8814_ALIGN_SWAP);
3234 lanphy_write_page_reg(phydev, 2, LAN8814_ALIGN_SWAP, val);
3237 lan8814_setup_led(phydev, lan8814->led_mode);
3247 static int lan8814_release_coma_mode(struct phy_device *phydev)
3251 gpiod = devm_gpiod_get_optional(&phydev->mdio.dev, "coma-mode",
3263 static int lan8814_probe(struct phy_device *phydev)
3265 const struct kszphy_type *type = phydev->drv->driver_data;
3270 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
3274 phydev->priv = priv;
3278 kszphy_parse_led_mode(phydev);
3283 addr = lanphy_read_page_reg(phydev, 4, 0) & 0x1F;
3284 devm_phy_package_join(&phydev->mdio.dev, phydev,
3287 if (phy_package_init_once(phydev)) {
3288 err = lan8814_release_coma_mode(phydev);
3292 err = lan8814_ptp_probe_once(phydev);
3297 lan8814_ptp_init(phydev);
3341 static int lan8841_config_init(struct phy_device *phydev)
3345 ret = ksz9131_config_init(phydev);
3350 phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3355 phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3361 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3363 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3365 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3367 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3369 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3371 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3375 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3377 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3381 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
3384 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
3391 ret = phy_read_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3394 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
3397 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
3408 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
3413 phy_write_mmd(phydev, MDIO_MMD_PMAPMD,
3415 phy_write_mmd(phydev, LAN8841_MMD_TIMER_REG,
3427 static int lan8841_config_intr(struct phy_device *phydev)
3431 phy_modify(phydev, LAN8841_OUTPUT_CTRL,
3434 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
3435 err = phy_read(phydev, LAN8814_INTS);
3444 err = phy_write(phydev, LAN8814_INTC,
3447 err = phy_write(phydev, LAN8814_INTC, 0);
3451 err = phy_read(phydev, LAN8814_INTS);
3467 struct phy_device *phydev = ptp_priv->phydev;
3469 *nsec = phy_read_mmd(phydev, 2, LAN8841_PTP_TX_EGRESS_NS_HI);
3474 *nsec = *nsec | phy_read_mmd(phydev, 2, LAN8841_PTP_TX_EGRESS_NS_LO);
3476 *sec = phy_read_mmd(phydev, 2, LAN8841_PTP_TX_EGRESS_SEC_HI);
3478 *sec = *sec | phy_read_mmd(phydev, 2, LAN8841_PTP_TX_EGRESS_SEC_LO);
3480 *seq = phy_read_mmd(phydev, 2, LAN8841_PTP_TX_MSG_HEADER2);
3501 struct phy_device *phydev = ptp_priv->phydev;
3505 phy_read_mmd(phydev, 2, LAN8841_PTP_TX_MSG_HEADER2);
3507 phy_read_mmd(phydev, 2, LAN8841_PTP_INT_STS);
3524 struct phy_device *phydev = ptp_priv->phydev;
3533 tmp = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_CAP_STS);
3537 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_GPIO_SEL,
3544 sec = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_RE_LTC_SEC_HI_CAP);
3546 sec |= phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_RE_LTC_SEC_LO_CAP);
3548 nsec = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_RE_LTC_NS_HI_CAP) & 0x3fff;
3550 nsec |= phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_RE_LTC_NS_LO_CAP);
3552 sec = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_FE_LTC_SEC_HI_CAP);
3554 sec |= phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_FE_LTC_SEC_LO_CAP);
3556 nsec = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_FE_LTC_NS_HI_CAP) & 0x3fff;
3558 nsec |= phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_FE_LTC_NS_LO_CAP);
3561 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_GPIO_SEL, 0);
3571 static void lan8841_handle_ptp_interrupt(struct phy_device *phydev)
3573 struct kszphy_priv *priv = phydev->priv;
3578 status = phy_read_mmd(phydev, 2, LAN8841_PTP_INT_STS);
3598 static irqreturn_t lan8841_handle_interrupt(struct phy_device *phydev)
3603 irq_status = phy_read(phydev, LAN8814_INTS);
3605 phy_error(phydev);
3610 phy_trigger_machine(phydev);
3615 lan8841_handle_ptp_interrupt(phydev);
3657 struct phy_device *phydev = ptp_priv->phydev;
3661 phy_modify_mmd(phydev, 2, LAN8841_PTP_INT_EN,
3671 phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3681 phy_modify_mmd(phydev, 2, LAN8841_PTP_INT_EN,
3686 phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3702 struct phy_device *phydev = ptp_priv->phydev;
3751 phy_write_mmd(phydev, 2, LAN8841_PTP_RX_PARSE_CONFIG, rxcfg);
3752 phy_write_mmd(phydev, 2, LAN8841_PTP_TX_PARSE_CONFIG, txcfg);
3756 phy_write_mmd(phydev, 2, LAN8841_PTP_RX_TIMESTAMP_EN, pkt_ts_enable);
3757 phy_write_mmd(phydev, 2, LAN8841_PTP_TX_TIMESTAMP_EN, pkt_ts_enable);
3760 phy_modify_mmd(phydev, 2, LAN8841_PTP_TX_MOD,
3831 struct phy_device *phydev = ptp_priv->phydev;
3834 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_SEC_HI(event),
3839 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_SEC_LO(event),
3844 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_NS_HI(event) & 0x3fff,
3849 return phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_NS_LO(event),
3870 struct phy_device *phydev = ptp_priv->phydev;
3873 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_RELOAD_SEC_HI(event),
3878 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_RELOAD_SEC_LO(event),
3883 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_RELOAD_NS_HI(event) & 0x3fff,
3888 return phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_RELOAD_NS_LO(event),
3904 struct phy_device *phydev = ptp_priv->phydev;
3910 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_SEC_LO, lower_16_bits(ts->tv_sec));
3911 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_SEC_MID, upper_16_bits(ts->tv_sec));
3912 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_SEC_HI, upper_32_bits(ts->tv_sec) & 0xffff);
3913 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_NS_LO, lower_16_bits(ts->tv_nsec));
3914 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_NS_HI, upper_16_bits(ts->tv_nsec) & 0x3fff);
3917 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,
3941 struct phy_device *phydev = ptp_priv->phydev;
3947 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,
3951 s = phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_HI);
3953 s |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_MID);
3955 s |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_LO);
3957 ns = phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_NS_HI) & 0x3fff;
3959 ns |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_NS_LO);
3971 struct phy_device *phydev = ptp_priv->phydev;
3976 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,
3980 s = phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_HI);
3982 s |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_MID);
3984 s |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_LO);
4000 struct phy_device *phydev = ptp_priv->phydev;
4052 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_STEP_ADJ_LO, sec);
4053 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_STEP_ADJ_HI,
4055 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,
4060 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_STEP_ADJ_LO,
4062 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_STEP_ADJ_HI,
4064 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,
4086 struct phy_device *phydev = ptp_priv->phydev;
4102 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_RATE_ADJ_HI,
4105 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_RATE_ADJ_LO, lower_16_bits(rate));
4133 struct phy_device *phydev = ptp_priv->phydev;
4136 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin));
4140 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_DIR, BIT(pin));
4144 return phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin));
4149 struct phy_device *phydev = ptp_priv->phydev;
4152 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin));
4156 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_DIR, BIT(pin));
4160 return phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin));
4179 struct phy_device *phydev = ptp_priv->phydev;
4189 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL1, tmp);
4192 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL2, tmp);
4204 return phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_EN, tmp);
4210 struct phy_device *phydev = ptp_priv->phydev;
4216 ret = phy_modify_mmd(phydev, 2, LAN8841_PTP_GENERAL_CONFIG,
4222 ret = phy_modify_mmd(phydev, 2, LAN8841_PTP_GENERAL_CONFIG,
4240 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL1,
4243 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL2,
4269 struct phy_device *phydev = ptp_priv->phydev;
4301 phydev_name(phydev));
4307 phydev_name(phydev));
4356 phydev_name(phydev));
4393 struct phy_device *phydev = ptp_priv->phydev;
4398 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin));
4402 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin));
4411 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_GPIO_CAP_EN, tmp);
4416 return phy_modify_mmd(phydev, 2, LAN8841_PTP_INT_EN,
4423 struct phy_device *phydev = ptp_priv->phydev;
4427 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin));
4431 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin));
4436 ret = phy_modify_mmd(phydev, 2, LAN8841_PTP_GPIO_CAP_EN,
4444 return phy_modify_mmd(phydev, 2, LAN8841_PTP_INT_EN,
4527 static int lan8841_probe(struct phy_device *phydev)
4533 err = kszphy_probe(phydev);
4537 if (phy_read_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4540 phydev->interface = PHY_INTERFACE_MODE_RGMII_RXID;
4546 priv = phydev->priv;
4549 ptp_priv->pin_config = devm_kcalloc(&phydev->mdio.dev,
4567 &phydev->mdio.dev);
4569 phydev_err(phydev, "ptp_clock_register failed: %lu\n",
4579 ptp_priv->phydev = phydev;
4588 phydev->mii_ts = &ptp_priv->mii_ts;
4593 static int lan8841_suspend(struct phy_device *phydev)
4595 struct kszphy_priv *priv = phydev->priv;
4600 return genphy_suspend(phydev);