Lines Matching defs:phydev
145 bool (*has_downshift)(struct phy_device *phydev);
147 int (*get_mactype)(struct phy_device *phydev);
148 int (*set_mactype)(struct phy_device *phydev, int mactype);
150 int (*init_interface)(struct phy_device *phydev, int mactype);
153 int (*hwmon_read_temp_reg)(struct phy_device *phydev);
169 static const struct mv3310_chip *to_mv3310_chip(struct phy_device *phydev)
171 return phydev->drv->driver_data;
186 static int mv3310_hwmon_read_temp_reg(struct phy_device *phydev)
188 return phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP);
191 static int mv2110_hwmon_read_temp_reg(struct phy_device *phydev)
193 return phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_TEMP);
199 struct phy_device *phydev = dev_get_drvdata(dev);
200 const struct mv3310_chip *chip = to_mv3310_chip(phydev);
209 temp = chip->hwmon_read_temp_reg(phydev);
257 static int mv3310_hwmon_config(struct phy_device *phydev, bool enable)
262 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310)
265 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP,
272 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL,
276 static int mv3310_hwmon_probe(struct phy_device *phydev)
278 struct device *dev = &phydev->mdio.dev;
279 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
295 ret = mv3310_hwmon_config(phydev, true);
300 priv->hwmon_name, phydev,
306 static inline int mv3310_hwmon_config(struct phy_device *phydev, bool enable)
311 static int mv3310_hwmon_probe(struct phy_device *phydev)
317 static int mv3310_power_down(struct phy_device *phydev)
319 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
323 static int mv3310_power_up(struct phy_device *phydev)
325 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
328 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
338 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310 ||
342 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
346 static int mv3310_reset(struct phy_device *phydev, u32 unit)
350 err = phy_modify_mmd(phydev, MDIO_MMD_PCS, unit + MDIO_CTRL1,
355 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PCS,
361 static int mv3310_get_downshift(struct phy_device *phydev, u8 *ds)
363 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
369 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC1);
382 static int mv3310_set_downshift(struct phy_device *phydev, u8 ds)
384 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
392 return phy_clear_bits_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC1,
411 err = phy_modify_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC2,
421 return phy_modify_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC1,
426 static int mv3310_get_edpd(struct phy_device *phydev, u16 *edpd)
430 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1);
448 static int mv3310_set_edpd(struct phy_device *phydev, u16 edpd)
471 err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1,
474 err = mv3310_reset(phydev, MV_PCS_BASE_T);
481 struct phy_device *phydev = upstream;
486 sfp_parse_support(phydev->sfp_bus, id, support, interfaces);
487 iface = sfp_select_interface(phydev->sfp_bus, support);
490 dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n");
502 static int mv3310_probe(struct phy_device *phydev)
504 const struct mv3310_chip *chip = to_mv3310_chip(phydev);
509 if (!phydev->is_c45 ||
510 (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask)
513 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_BOOT);
518 dev_warn(&phydev->mdio.dev,
523 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
527 dev_set_drvdata(&phydev->mdio.dev, priv);
529 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER0);
535 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER1);
541 phydev_info(phydev, "Firmware version %u.%u.%u.%u\n",
546 priv->has_downshift = chip->has_downshift(phydev);
549 ret = mv3310_power_down(phydev);
553 ret = mv3310_hwmon_probe(phydev);
559 return phy_sfp_probe(phydev, &mv3310_sfp_ops);
562 static void mv3310_remove(struct phy_device *phydev)
564 mv3310_hwmon_config(phydev, false);
567 static int mv3310_suspend(struct phy_device *phydev)
569 return mv3310_power_down(phydev);
572 static int mv3310_resume(struct phy_device *phydev)
576 ret = mv3310_power_up(phydev);
580 return mv3310_hwmon_config(phydev, true);
590 static bool mv3310_has_pma_ngbaset_quirk(struct phy_device *phydev)
592 if (!(phydev->c45_ids.devices_in_package & MDIO_DEVS_PMAPMD))
596 return (phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &
600 static int mv2110_get_mactype(struct phy_device *phydev)
604 mactype = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_21X0_PORT_CTRL);
611 static int mv2110_set_mactype(struct phy_device *phydev, int mactype)
616 err = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_21X0_PORT_CTRL,
623 err = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MV_AN_21X0_SERDES_CTRL2,
629 err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_AN,
637 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MV_AN_21X0_SERDES_CTRL2,
654 static int mv3310_get_mactype(struct phy_device *phydev)
658 mactype = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL);
665 static int mv3310_set_mactype(struct phy_device *phydev, int mactype)
670 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
676 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
705 static int mv2110_init_interface(struct phy_device *phydev, int mactype)
707 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
727 static int mv3310_init_interface(struct phy_device *phydev, int mactype)
729 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
756 static int mv3340_init_interface(struct phy_device *phydev, int mactype)
758 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
766 err = mv3310_init_interface(phydev, mactype);
771 static int mv3310_config_init(struct phy_device *phydev)
773 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
774 const struct mv3310_chip *chip = to_mv3310_chip(phydev);
778 if (!test_bit(phydev->interface, priv->supported_interfaces))
781 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
784 err = mv3310_power_up(phydev);
791 if (!phy_interface_empty(phydev->host_interfaces)) {
792 mactype = chip->select_mactype(phydev->host_interfaces);
794 phydev_info(phydev, "Changing MACTYPE to %i\n",
796 err = chip->set_mactype(phydev, mactype);
802 mactype = chip->get_mactype(phydev);
806 err = chip->init_interface(phydev, mactype);
808 phydev_err(phydev, "MACTYPE configuration invalid\n");
813 err = mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);
818 err = mv3310_set_downshift(phydev, DOWNSHIFT_DEV_DEFAULT_COUNT);
825 static int mv3310_get_features(struct phy_device *phydev)
829 ret = genphy_c45_pma_read_abilities(phydev);
833 if (mv3310_has_pma_ngbaset_quirk(phydev)) {
834 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
840 phydev->supported,
844 phydev->supported,
851 static int mv3310_config_mdix(struct phy_device *phydev)
856 switch (phydev->mdix_ctrl) {
870 err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1,
873 err = mv3310_reset(phydev, MV_PCS_BASE_T);
878 static int mv3310_config_aneg(struct phy_device *phydev)
884 ret = mv3310_config_mdix(phydev);
888 if (phydev->autoneg == AUTONEG_DISABLE)
889 return genphy_c45_pma_setup_forced(phydev);
891 ret = genphy_c45_an_config_aneg(phydev);
900 reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
901 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MV_AN_CTRL1000,
908 return genphy_c45_check_and_restart_aneg(phydev, changed);
911 static int mv3310_aneg_done(struct phy_device *phydev)
915 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
922 return genphy_c45_aneg_done(phydev);
925 static void mv3310_update_interface(struct phy_device *phydev)
927 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
929 if (!phydev->link)
940 phydev->interface = priv->const_interface;
947 * Florian suggests setting phydev->interface to communicate this to the
950 switch (phydev->speed) {
952 phydev->interface = priv->const_interface;
955 phydev->interface = PHY_INTERFACE_MODE_5GBASER;
958 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
963 phydev->interface = PHY_INTERFACE_MODE_SGMII;
971 static int mv3310_read_status_10gbaser(struct phy_device *phydev)
973 phydev->link = 1;
974 phydev->speed = SPEED_10000;
975 phydev->duplex = DUPLEX_FULL;
976 phydev->port = PORT_FIBRE;
981 static int mv3310_read_status_copper(struct phy_device *phydev)
985 val = genphy_c45_read_link(phydev);
989 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
993 cssr1 = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSSR1);
999 phydev->link = 0;
1010 phydev->speed = SPEED_10000;
1014 phydev->speed = SPEED_5000;
1018 phydev->speed = SPEED_2500;
1022 phydev->speed = SPEED_1000;
1026 phydev->speed = SPEED_100;
1030 phydev->speed = SPEED_10;
1034 phydev->duplex = cssr1 & MV_PCS_CSSR1_DUPLEX_FULL ?
1036 phydev->port = PORT_TP;
1037 phydev->mdix = cssr1 & MV_PCS_CSSR1_MDIX ?
1041 val = genphy_c45_read_lpa(phydev);
1046 val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000);
1050 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val);
1053 phy_resolve_aneg_pause(phydev);
1059 static int mv3310_read_status(struct phy_device *phydev)
1063 phydev->speed = SPEED_UNKNOWN;
1064 phydev->duplex = DUPLEX_UNKNOWN;
1065 linkmode_zero(phydev->lp_advertising);
1066 phydev->link = 0;
1067 phydev->pause = 0;
1068 phydev->asym_pause = 0;
1069 phydev->mdix = ETH_TP_MDI_INVALID;
1071 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
1076 err = mv3310_read_status_10gbaser(phydev);
1078 err = mv3310_read_status_copper(phydev);
1082 if (phydev->link)
1083 mv3310_update_interface(phydev);
1088 static int mv3310_get_tunable(struct phy_device *phydev,
1093 return mv3310_get_downshift(phydev, data);
1095 return mv3310_get_edpd(phydev, data);
1101 static int mv3310_set_tunable(struct phy_device *phydev,
1106 return mv3310_set_downshift(phydev, *(u8 *)data);
1108 return mv3310_set_edpd(phydev, *(u16 *)data);
1114 static bool mv3310_has_downshift(struct phy_device *phydev)
1116 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
1210 static int mv3310_get_number_of_ports(struct phy_device *phydev)
1214 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_PORT_INFO);
1224 static int mv3310_match_phy_device(struct phy_device *phydev)
1226 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &
1230 return mv3310_get_number_of_ports(phydev) == 1;
1233 static int mv3340_match_phy_device(struct phy_device *phydev)
1235 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &
1239 return mv3310_get_number_of_ports(phydev) == 4;
1242 static int mv211x_match_phy_device(struct phy_device *phydev, bool has_5g)
1246 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &
1250 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_SPEED);
1257 static int mv2110_match_phy_device(struct phy_device *phydev)
1259 return mv211x_match_phy_device(phydev, true);
1262 static int mv2111_match_phy_device(struct phy_device *phydev)
1264 return mv211x_match_phy_device(phydev, false);
1267 static void mv3110_get_wol(struct phy_device *phydev,
1275 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_WOL_CTRL);
1283 static int mv3110_set_wol(struct phy_device *phydev,
1290 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
1297 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
1299 ((phydev->attached_dev->dev_addr[5] << 8) |
1300 phydev->attached_dev->dev_addr[4]));
1304 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
1306 ((phydev->attached_dev->dev_addr[3] << 8) |
1307 phydev->attached_dev->dev_addr[2]));
1311 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
1313 ((phydev->attached_dev->dev_addr[1] << 8) |
1314 phydev->attached_dev->dev_addr[0]));
1319 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
1327 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2,
1336 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,