Lines Matching defs:phydev
156 static int dp83869_read_status(struct phy_device *phydev)
158 struct dp83869_private *dp83869 = phydev->priv;
161 ret = genphy_read_status(phydev);
165 if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported)) {
166 if (phydev->link) {
168 phydev->speed = SPEED_100;
170 phydev->speed = SPEED_UNKNOWN;
171 phydev->duplex = DUPLEX_UNKNOWN;
178 static int dp83869_ack_interrupt(struct phy_device *phydev)
180 int err = phy_read(phydev, MII_DP83869_ISR);
188 static int dp83869_config_intr(struct phy_device *phydev)
192 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
193 err = dp83869_ack_interrupt(phydev);
197 micr_status = phy_read(phydev, MII_DP83869_MICR);
209 err = phy_write(phydev, MII_DP83869_MICR, micr_status);
211 err = phy_write(phydev, MII_DP83869_MICR, micr_status);
215 err = dp83869_ack_interrupt(phydev);
221 static irqreturn_t dp83869_handle_interrupt(struct phy_device *phydev)
225 irq_status = phy_read(phydev, MII_DP83869_ISR);
227 phy_error(phydev);
231 irq_enabled = phy_read(phydev, MII_DP83869_MICR);
233 phy_error(phydev);
240 phy_trigger_machine(phydev);
245 static int dp83869_set_wol(struct phy_device *phydev,
248 struct net_device *ndev = phydev->attached_dev;
253 val_rxcfg = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG);
257 val_micr = phy_read(phydev, MII_DP83869_MICR);
273 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
279 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
285 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
297 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
303 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
308 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
333 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG, val_rxcfg);
337 return phy_write(phydev, MII_DP83869_MICR, val_micr);
340 static void dp83869_get_wol(struct phy_device *phydev,
349 value = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG);
351 phydev_err(phydev, "Failed to read RX CFG\n");
365 sopass_val = phy_read_mmd(phydev, DP83869_DEVADDR,
368 phydev_err(phydev, "Failed to read RX SOP 1\n");
375 sopass_val = phy_read_mmd(phydev, DP83869_DEVADDR,
378 phydev_err(phydev, "Failed to read RX SOP 2\n");
385 sopass_val = phy_read_mmd(phydev, DP83869_DEVADDR,
388 phydev_err(phydev, "Failed to read RX SOP 3\n");
402 static int dp83869_get_downshift(struct phy_device *phydev, u8 *data)
406 val = phy_read(phydev, DP83869_CFG2);
435 static int dp83869_set_downshift(struct phy_device *phydev, u8 cnt)
443 return phy_clear_bits(phydev, DP83869_CFG2,
460 phydev_err(phydev,
468 return phy_modify(phydev, DP83869_CFG2,
473 static int dp83869_get_tunable(struct phy_device *phydev,
478 return dp83869_get_downshift(phydev, data);
484 static int dp83869_set_tunable(struct phy_device *phydev,
489 return dp83869_set_downshift(phydev, *(const u8 *)data);
495 static int dp83869_config_port_mirroring(struct phy_device *phydev)
497 struct dp83869_private *dp83869 = phydev->priv;
500 return phy_set_bits_mmd(phydev, DP83869_DEVADDR,
504 return phy_clear_bits_mmd(phydev, DP83869_DEVADDR,
509 static int dp83869_set_strapped_mode(struct phy_device *phydev)
511 struct dp83869_private *dp83869 = phydev->priv;
514 val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_STRAP_STS1);
528 static int dp83869_of_init(struct phy_device *phydev)
530 struct dp83869_private *dp83869 = phydev->priv;
531 struct device *dev = &phydev->mdio.dev;
553 ret = dp83869_set_strapped_mode(phydev);
567 ret = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_STRAP_STS1);
587 dp83869->rx_int_delay = phy_get_internal_delay(phydev, dev,
593 dp83869->tx_int_delay = phy_get_internal_delay(phydev, dev,
602 static int dp83869_of_init(struct phy_device *phydev)
604 return dp83869_set_strapped_mode(phydev);
608 static int dp83869_configure_rgmii(struct phy_device *phydev,
613 if (phy_interface_is_rgmii(phydev)) {
614 val = phy_read(phydev, MII_DP83869_PHYCTRL);
622 ret = phy_write(phydev, MII_DP83869_PHYCTRL, val);
628 ret = phy_modify_mmd(phydev, DP83869_DEVADDR,
637 static int dp83869_configure_fiber(struct phy_device *phydev,
644 linkmode_and(phydev->advertising, phydev->advertising,
645 phydev->supported);
647 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported);
648 linkmode_set_bit(ADVERTISED_FIBRE, phydev->advertising);
652 phydev->supported);
655 phydev->supported);
657 phydev->supported);
660 bmcr = phy_read(phydev, MII_BMCR);
664 phydev->autoneg = AUTONEG_DISABLE;
665 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
666 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->advertising);
669 ret = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0);
676 linkmode_or(phydev->advertising, phydev->advertising,
677 phydev->supported);
682 static int dp83869_configure_mode(struct phy_device *phydev,
696 if (phydev->interface == PHY_INTERFACE_MODE_MII) {
701 phydev_err(phydev, "selected op-mode is not valid with MII mode\n");
706 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE,
711 ret = phy_write(phydev, MII_BMCR, MII_DP83869_BMCR_DEFAULT);
721 ret = phy_write(phydev, MII_DP83869_PHYCTRL,
726 ret = phy_write(phydev, MII_CTRL1000, DP83869_CFG1_DEFAULT);
730 ret = dp83869_configure_rgmii(phydev, dp83869);
735 ret = phy_modify_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE,
741 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
748 ret = phy_write(phydev, MII_DP83869_PHYCTRL,
753 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
759 ret = phy_write(phydev, MII_DP83869_PHYCTRL,
765 ret = phy_write(phydev, MII_DP83869_PHYCTRL,
770 ret = phy_write(phydev, MII_CTRL1000, DP83869_CFG1_DEFAULT);
774 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
782 ret = dp83869_configure_fiber(phydev, dp83869);
791 static int dp83869_config_init(struct phy_device *phydev)
793 struct dp83869_private *dp83869 = phydev->priv;
797 ret = phy_modify(phydev, DP83869_CFG2, DP83869_DOWNSHIFT_EN,
802 ret = dp83869_configure_mode(phydev, dp83869);
807 if (phy_interrupt_is_valid(phydev)) {
808 val = phy_read(phydev, DP83869_CFG4);
810 phy_write(phydev, DP83869_CFG4, val);
814 dp83869_config_port_mirroring(phydev);
818 ret = phy_modify_mmd(phydev,
824 if (phy_interface_is_rgmii(phydev)) {
825 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIIDCTL,
831 val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL);
835 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
839 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
842 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
845 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL,
852 static int dp83869_probe(struct phy_device *phydev)
857 dp83869 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83869),
862 phydev->priv = dp83869;
864 ret = dp83869_of_init(phydev);
870 phydev->port = PORT_FIBRE;
872 return dp83869_config_init(phydev);
875 static int dp83869_phy_reset(struct phy_device *phydev)
879 ret = phy_write(phydev, DP83869_CTRL, DP83869_SW_RESET);
888 return dp83869_config_init(phydev);