Lines Matching defs:phydev
181 static int dp83867_ack_interrupt(struct phy_device *phydev)
183 int err = phy_read(phydev, MII_DP83867_ISR);
191 static int dp83867_set_wol(struct phy_device *phydev,
194 struct net_device *ndev = phydev->attached_dev;
198 val_rxcfg = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
199 val_micr = phy_read(phydev, MII_DP83867_MICR);
212 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD1,
214 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD2,
216 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD3,
225 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1,
227 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP2,
229 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP3,
251 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG, val_rxcfg);
252 phy_write(phydev, MII_DP83867_MICR, val_micr);
257 static void dp83867_get_wol(struct phy_device *phydev,
266 value = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
278 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
283 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
288 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
300 static int dp83867_config_intr(struct phy_device *phydev)
304 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
305 err = dp83867_ack_interrupt(phydev);
309 micr_status = phy_read(phydev, MII_DP83867_MICR);
321 err = phy_write(phydev, MII_DP83867_MICR, micr_status);
324 err = phy_write(phydev, MII_DP83867_MICR, micr_status);
328 err = dp83867_ack_interrupt(phydev);
334 static irqreturn_t dp83867_handle_interrupt(struct phy_device *phydev)
338 irq_status = phy_read(phydev, MII_DP83867_ISR);
340 phy_error(phydev);
344 irq_enabled = phy_read(phydev, MII_DP83867_MICR);
346 phy_error(phydev);
353 phy_trigger_machine(phydev);
358 static int dp83867_read_status(struct phy_device *phydev)
360 int status = phy_read(phydev, MII_DP83867_PHYSTS);
363 ret = genphy_read_status(phydev);
371 phydev->duplex = DUPLEX_FULL;
373 phydev->duplex = DUPLEX_HALF;
376 phydev->speed = SPEED_1000;
378 phydev->speed = SPEED_100;
380 phydev->speed = SPEED_10;
385 static int dp83867_get_downshift(struct phy_device *phydev, u8 *data)
389 val = phy_read(phydev, DP83867_CFG2);
418 static int dp83867_set_downshift(struct phy_device *phydev, u8 cnt)
426 return phy_clear_bits(phydev, DP83867_CFG2,
443 phydev_err(phydev,
451 return phy_modify(phydev, DP83867_CFG2,
456 static int dp83867_get_tunable(struct phy_device *phydev,
461 return dp83867_get_downshift(phydev, data);
467 static int dp83867_set_tunable(struct phy_device *phydev,
472 return dp83867_set_downshift(phydev, *(const u8 *)data);
478 static int dp83867_config_port_mirroring(struct phy_device *phydev)
480 struct dp83867_private *dp83867 = phydev->priv;
483 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
486 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
491 static int dp83867_verify_rgmii_cfg(struct phy_device *phydev)
493 struct dp83867_private *dp83867 = phydev->priv;
498 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
499 const u16 val = phy_read_mmd(phydev, DP83867_DEVADDR,
508 phydev_warn(phydev,
515 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
516 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) &&
518 phydev_err(phydev, "ti,rx-internal-delay must be specified\n");
523 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
524 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) &&
526 phydev_err(phydev, "ti,tx-internal-delay must be specified\n");
534 static int dp83867_of_init_io_impedance(struct phy_device *phydev)
536 struct dp83867_private *dp83867 = phydev->priv;
537 struct device *dev = &phydev->mdio.dev;
547 return phydev_err_probe(phydev, ret,
571 phydev_err(phydev, "nvmem cell 'io_impedance_ctrl' contents out of range\n");
579 static int dp83867_of_init(struct phy_device *phydev)
581 struct dp83867_private *dp83867 = phydev->priv;
582 struct device *dev = &phydev->mdio.dev;
600 phydev_err(phydev, "ti,clk-output-sel value %u out of range\n",
606 ret = dp83867_of_init_io_impedance(phydev);
620 phydev_err(phydev,
630 phydev_err(phydev,
653 phydev_err(phydev, "tx-fifo-depth value %u out of range\n",
664 phydev_err(phydev, "rx-fifo-depth value %u out of range\n",
672 static int dp83867_of_init(struct phy_device *phydev)
674 struct dp83867_private *dp83867 = phydev->priv;
682 delay = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL);
704 static int dp83867_suspend(struct phy_device *phydev)
707 if (phy_interrupt_is_valid(phydev)) {
708 phydev->interrupts = PHY_INTERRUPT_DISABLED;
709 dp83867_config_intr(phydev);
712 return genphy_suspend(phydev);
715 static int dp83867_resume(struct phy_device *phydev)
718 if (phy_interrupt_is_valid(phydev)) {
719 phydev->interrupts = PHY_INTERRUPT_ENABLED;
720 dp83867_config_intr(phydev);
723 genphy_resume(phydev);
728 static int dp83867_probe(struct phy_device *phydev)
732 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
737 phydev->priv = dp83867;
739 return dp83867_of_init(phydev);
742 static int dp83867_config_init(struct phy_device *phydev)
744 struct dp83867_private *dp83867 = phydev->priv;
749 ret = phy_modify(phydev, DP83867_CFG2, DP83867_DOWNSHIFT_EN,
754 ret = dp83867_verify_rgmii_cfg(phydev);
760 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
763 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS2);
769 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
777 if (phy_interface_is_rgmii(phydev) ||
778 phydev->interface == PHY_INTERFACE_MODE_SGMII) {
779 val = phy_read(phydev, MII_DP83867_PHYCTRL);
787 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
793 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
798 if (phy_interface_is_rgmii(phydev)) {
799 val = phy_read(phydev, MII_DP83867_PHYCTRL);
813 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
817 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
828 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
831 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
834 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
837 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
840 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
849 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
855 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
859 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
866 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
877 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
885 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL);
894 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val);
901 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
905 val = phy_read(phydev, DP83867_CFG3);
907 if (phy_interrupt_is_valid(phydev))
911 phy_write(phydev, DP83867_CFG3, val);
914 dp83867_config_port_mirroring(phydev);
928 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
935 static int dp83867_phy_reset(struct phy_device *phydev)
939 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET);
945 err = phy_modify(phydev, MII_DP83867_PHYCTRL,
954 err = phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_DSP_FFE_CFG,
959 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESTART);
968 static void dp83867_link_change_notify(struct phy_device *phydev)
981 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
984 val = phy_clear_bits(phydev, DP83867_CFG2,
989 phy_set_bits(phydev, DP83867_CFG2,
994 static int dp83867_loopback(struct phy_device *phydev, bool enable)
996 return phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK,
1001 dp83867_led_brightness_set(struct phy_device *phydev,
1015 return phy_modify(phydev, DP83867_LEDCR2,