Lines Matching defs:dp83867
19 #include <dt-bindings/net/ti-dp83867.h>
480 struct dp83867_private *dp83867 = phydev->priv;
482 if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)
493 struct dp83867_private *dp83867 = phydev->priv;
517 dp83867->rx_id_delay == DP83867_RGMII_RX_CLK_DELAY_INV) {
525 dp83867->tx_id_delay == DP83867_RGMII_TX_CLK_DELAY_INV) {
536 struct dp83867_private *dp83867 = phydev->priv;
552 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
554 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
556 dp83867->io_impedance = -1; /* leave at default */
574 dp83867->io_impedance = val;
581 struct dp83867_private *dp83867 = phydev->priv;
591 &dp83867->clk_output_sel);
594 dp83867->set_clk_output = true;
598 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK &&
599 dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) {
601 dp83867->clk_output_sel);
610 dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node,
611 "ti,dp83867-rxctrl-strap-quirk");
613 dp83867->sgmii_ref_clk_en = of_property_read_bool(of_node,
616 dp83867->rx_id_delay = DP83867_RGMII_RX_CLK_DELAY_INV;
618 &dp83867->rx_id_delay);
619 if (!ret && dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) {
622 dp83867->rx_id_delay);
626 dp83867->tx_id_delay = DP83867_RGMII_TX_CLK_DELAY_INV;
628 &dp83867->tx_id_delay);
629 if (!ret && dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) {
632 dp83867->tx_id_delay);
637 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN;
640 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS;
643 &dp83867->tx_fifo_depth);
646 &dp83867->tx_fifo_depth);
648 dp83867->tx_fifo_depth =
652 if (dp83867->tx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
654 dp83867->tx_fifo_depth);
659 &dp83867->rx_fifo_depth);
661 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
663 if (dp83867->rx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
665 dp83867->rx_fifo_depth);
674 struct dp83867_private *dp83867 = phydev->priv;
683 dp83867->rx_id_delay = delay & DP83867_RGMII_RX_CLK_DELAY_MAX;
684 dp83867->tx_id_delay = (delay >> DP83867_RGMII_TX_CLK_DELAY_SHIFT) &
691 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN / 2;
697 dp83867->tx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
698 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
730 struct dp83867_private *dp83867;
732 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
734 if (!dp83867)
737 phydev->priv = dp83867;
744 struct dp83867_private *dp83867 = phydev->priv;
759 if (dp83867->rxctrl_strap_quirk)
784 val |= (dp83867->tx_fifo_depth <<
789 val |= (dp83867->rx_fifo_depth <<
843 if (dp83867->rx_id_delay != DP83867_RGMII_RX_CLK_DELAY_INV)
844 delay |= dp83867->rx_id_delay;
845 if (dp83867->tx_id_delay != DP83867_RGMII_TX_CLK_DELAY_INV)
846 delay |= dp83867->tx_id_delay <<
854 if (dp83867->io_impedance >= 0)
857 dp83867->io_impedance);
890 if (dp83867->sgmii_ref_clk_en)
900 if (dp83867->rxctrl_strap_quirk)
913 if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
917 if (dp83867->set_clk_output) {
920 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) {
924 val = dp83867->clk_output_sel <<