Lines Matching defs:DP83867_DEVADDR
22 #define DP83867_DEVADDR 0x1f
198 val_rxcfg = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
212 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD1,
214 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD2,
216 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD3,
225 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1,
227 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP2,
229 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP3,
251 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG, val_rxcfg);
266 value = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
278 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
283 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
288 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
483 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
486 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
499 const u16 val = phy_read_mmd(phydev, DP83867_DEVADDR,
682 delay = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL);
760 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
763 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS2);
769 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
813 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
828 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
840 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
849 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
855 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
866 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
877 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
885 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL);
894 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val);
901 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
928 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
954 err = phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_DSP_FFE_CFG,