Lines Matching defs:phydev
108 struct phy_device *phydev;
219 static inline int broadcast_write(struct phy_device *phydev, u32 regnum,
222 return mdiobus_write(phydev->mdio.bus, BROADCAST_ADDR, regnum, val);
226 static int ext_read(struct phy_device *phydev, int page, u32 regnum)
228 struct dp83640_private *dp83640 = phydev->priv;
232 broadcast_write(phydev, PAGESEL, page);
235 val = phy_read(phydev, regnum);
241 static void ext_write(int broadcast, struct phy_device *phydev,
244 struct dp83640_private *dp83640 = phydev->priv;
247 broadcast_write(phydev, PAGESEL, page);
251 broadcast_write(phydev, regnum, val);
253 phy_write(phydev, regnum, val);
308 struct phy_device *phydev = dp83640->phydev;
332 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig);
333 ext_write(0, phydev, PAGE4, PTP_CTL, val);
346 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig);
350 ext_write(0, phydev, PAGE4, PTP_CTL, val);
351 ext_write(0, phydev, PAGE4, PTP_TDR, nsec & 0xffff); /* ns[15:0] */
352 ext_write(0, phydev, PAGE4, PTP_TDR, nsec >> 16); /* ns[31:16] */
353 ext_write(0, phydev, PAGE4, PTP_TDR, sec & 0xffff); /* sec[15:0] */
354 ext_write(0, phydev, PAGE4, PTP_TDR, sec >> 16); /* sec[31:16] */
355 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff); /* ns[15:0] */
356 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16); /* ns[31:16] */
359 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff);
360 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16);
366 ext_write(0, phydev, PAGE4, PTP_CTL, val);
378 struct phy_device *phydev = clock->chosen->phydev;
399 ext_write(1, phydev, PAGE4, PTP_RATEH, hi);
400 ext_write(1, phydev, PAGE4, PTP_RATEL, lo);
411 struct phy_device *phydev = clock->chosen->phydev;
421 err = tdr_write(1, phydev, &ts, PTP_STEP_CLK);
433 struct phy_device *phydev = clock->chosen->phydev;
438 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_RD_CLK);
440 val[0] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[15:0] */
441 val[1] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[31:16] */
442 val[2] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[15:0] */
443 val[3] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[31:16] */
458 struct phy_device *phydev = clock->chosen->phydev;
463 err = tdr_write(1, phydev, ts, PTP_LOAD_CLK);
475 struct phy_device *phydev = clock->chosen->phydev;
511 ext_write(0, phydev, PAGE5, PTP_EVNT, evnt);
549 static void enable_status_frames(struct phy_device *phydev, bool on)
551 struct dp83640_private *dp83640 = phydev->priv;
562 ext_write(0, phydev, PAGE5, PSF_CFG0, cfg0);
563 ext_write(0, phydev, PAGE6, PSF_CFG1, ver);
567 if (!phydev->attached_dev) {
568 phydev_warn(phydev,
574 if (dev_mc_add(phydev->attached_dev, status_frame_dst))
575 phydev_warn(phydev, "failed to add mc address\n");
577 if (dev_mc_del(phydev->attached_dev, status_frame_dst))
578 phydev_warn(phydev, "failed to delete mc address\n");
615 static void enable_broadcast(struct phy_device *phydev, int init_page, int on)
619 phy_write(phydev, PAGESEL, 0);
620 val = phy_read(phydev, PHYCR2);
625 phy_write(phydev, PHYCR2, val);
626 phy_write(phydev, PAGESEL, init_page);
635 struct phy_device *master = clock->chosen->phydev;
651 enable_broadcast(tmp->phydev, clock->page, 1);
652 tmp->cfg0 = ext_read(tmp->phydev, PAGE5, PSF_CFG0);
653 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, 0);
654 ext_write(0, tmp->phydev, PAGE4, PTP_CTL, PTP_ENABLE);
669 ext_write(0, tmp->phydev, PAGE5, PTP_EVNT, evnt);
709 val = ext_read(tmp->phydev, PAGE4, PTP_STS);
710 phydev_info(tmp->phydev, "slave PTP_STS 0x%04hx\n", val);
711 val = ext_read(tmp->phydev, PAGE4, PTP_ESTS);
712 phydev_info(tmp->phydev, "slave PTP_ESTS 0x%04hx\n", val);
713 event_ts.ns_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
714 event_ts.ns_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
715 event_ts.sec_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
716 event_ts.sec_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
718 phydev_info(tmp->phydev, "slave offset %lld nanoseconds\n",
722 tdr_write(0, tmp->phydev, &ts, PTP_STEP_CLK);
729 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, tmp->cfg0);
1022 struct phy_device *phydev)
1027 if (chosen_phy == phydev->mdio.addr)
1086 static int dp83640_soft_reset(struct phy_device *phydev)
1090 ret = genphy_soft_reset(phydev);
1103 static int dp83640_config_init(struct phy_device *phydev)
1105 struct dp83640_private *dp83640 = phydev->priv;
1112 enable_broadcast(phydev, clock->page, 1);
1116 enable_status_frames(phydev, true);
1119 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_ENABLE);
1125 static int dp83640_ack_interrupt(struct phy_device *phydev)
1127 int err = phy_read(phydev, MII_DP83640_MISR);
1135 static int dp83640_config_intr(struct phy_device *phydev)
1141 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1142 err = dp83640_ack_interrupt(phydev);
1146 misr = phy_read(phydev, MII_DP83640_MISR);
1154 err = phy_write(phydev, MII_DP83640_MISR, misr);
1158 micr = phy_read(phydev, MII_DP83640_MICR);
1164 return phy_write(phydev, MII_DP83640_MICR, micr);
1166 micr = phy_read(phydev, MII_DP83640_MICR);
1172 err = phy_write(phydev, MII_DP83640_MICR, micr);
1176 misr = phy_read(phydev, MII_DP83640_MISR);
1184 err = phy_write(phydev, MII_DP83640_MISR, misr);
1188 return dp83640_ack_interrupt(phydev);
1192 static irqreturn_t dp83640_handle_interrupt(struct phy_device *phydev)
1196 irq_status = phy_read(phydev, MII_DP83640_MISR);
1198 phy_error(phydev);
1205 phy_trigger_machine(phydev);
1290 ext_write(0, dp83640->phydev, PAGE5, PTP_TXCFG0, txcfg0);
1291 ext_write(0, dp83640->phydev, PAGE5, PTP_RXCFG0, rxcfg0);
1423 static int dp83640_probe(struct phy_device *phydev)
1429 if (phydev->mdio.addr == BROADCAST_ADDR)
1432 clock = dp83640_clock_get_bus(phydev->mdio.bus);
1440 dp83640->phydev = phydev;
1452 phydev->mii_ts = &dp83640->mii_ts;
1453 phydev->priv = dp83640;
1461 if (choose_this_phy(clock, phydev)) {
1464 &phydev->mdio.dev);
1484 static void dp83640_remove(struct phy_device *phydev)
1488 struct dp83640_private *tmp, *dp83640 = phydev->priv;
1490 if (phydev->mdio.addr == BROADCAST_ADDR)
1493 phydev->mii_ts = NULL;
1495 enable_status_frames(phydev, false);