Lines Matching defs:phydev
24 #define BRCM_PHY_MODEL(phydev) \
25 ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
27 #define BRCM_PHY_REV(phydev) \
28 ((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask))
41 static bool bcm54xx_phy_can_wakeup(struct phy_device *phydev)
43 struct bcm54xx_phy_priv *priv = phydev->priv;
45 return phy_interrupt_is_valid(phydev) || priv->wake_irq >= 0;
48 static int bcm54xx_config_clock_delay(struct phy_device *phydev)
53 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
55 if (phydev->interface == PHY_INTERFACE_MODE_RGMII ||
56 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
60 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
61 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
65 rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
71 val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL);
72 if (phydev->interface == PHY_INTERFACE_MODE_RGMII ||
73 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
77 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
78 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
82 rc = bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val);
89 static int bcm54210e_config_init(struct phy_device *phydev)
93 bcm54xx_config_clock_delay(phydev);
95 if (phydev->dev_flags & PHY_BRCM_EN_MASTER_MODE) {
96 val = phy_read(phydev, MII_CTRL1000);
98 phy_write(phydev, MII_CTRL1000, val);
104 static int bcm54612e_config_init(struct phy_device *phydev)
108 bcm54xx_config_clock_delay(phydev);
111 if (!(phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED)) {
114 reg = bcm_phy_read_exp(phydev, BCM54612E_EXP_SPARE0);
115 err = bcm_phy_write_exp(phydev, BCM54612E_EXP_SPARE0,
125 static int bcm54616s_config_init(struct phy_device *phydev)
129 if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
130 phydev->interface != PHY_INTERFACE_MODE_1000BASEX)
135 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
140 rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
146 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE);
150 rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val);
155 rc = phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN);
161 val |= phydev->interface == PHY_INTERFACE_MODE_SGMII ?
164 rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val);
169 rc = phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN);
175 rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val);
180 return phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN);
184 static int bcm50610_a0_workaround(struct phy_device *phydev)
188 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH0,
194 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH3,
199 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75,
204 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP96,
209 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP97,
215 static int bcm54xx_phydsp_config(struct phy_device *phydev)
220 err = bcm54xx_auxctl_write(phydev,
227 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
228 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) {
230 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP08,
235 if (phydev->drv->phy_id == PHY_ID_BCM50610) {
236 err = bcm50610_a0_workaround(phydev);
242 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM57780) {
245 val = bcm_phy_read_exp(phydev, MII_BCM54XX_EXP_EXP75);
250 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75, val);
255 err2 = bcm54xx_auxctl_write(phydev,
263 static void bcm54xx_adjust_rxrefclk(struct phy_device *phydev)
270 if (BRCM_PHY_MODEL(phydev) != PHY_ID_BCM57780 &&
271 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610 &&
272 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610M &&
273 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54210E &&
274 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54810 &&
275 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54811)
278 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3);
284 if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
285 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
286 BRCM_PHY_REV(phydev) >= 0x3) {
293 if (phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) {
294 if (BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54811) {
302 if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
307 if (phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY) {
308 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54210E ||
309 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810 ||
310 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54811)
317 bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR3, val);
319 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_APD);
325 if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
331 bcm_phy_write_shadow(phydev, BCM54XX_SHD_APD, val);
334 static void bcm54xx_ptp_stop(struct phy_device *phydev)
336 struct bcm54xx_phy_priv *priv = phydev->priv;
342 static void bcm54xx_ptp_config_init(struct phy_device *phydev)
344 struct bcm54xx_phy_priv *priv = phydev->priv;
347 bcm_ptp_config_init(phydev);
350 static int bcm54xx_config_init(struct phy_device *phydev)
354 reg = phy_read(phydev, MII_BCM54XX_ECR);
360 err = phy_write(phydev, MII_BCM54XX_ECR, reg);
368 err = phy_write(phydev, MII_BCM54XX_IMR, reg);
372 if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
373 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
374 (phydev->dev_flags & PHY_BRCM_CLEAR_RGMII_MODE))
375 bcm_phy_write_shadow(phydev, BCM54XX_SHD_RGMII_MODE, 0);
377 bcm54xx_adjust_rxrefclk(phydev);
379 switch (BRCM_PHY_MODEL(phydev)) {
382 err = bcm54xx_config_clock_delay(phydev);
385 err = bcm54210e_config_init(phydev);
388 err = bcm54612e_config_init(phydev);
391 err = bcm54616s_config_init(phydev);
395 val = bcm_phy_read_exp(phydev,
398 err = bcm_phy_write_exp(phydev,
406 bcm54xx_phydsp_config(phydev);
416 if (!phy_on_sfp(phydev)) {
419 bcm_phy_write_shadow(phydev, BCM54XX_SHD_LEDS1, val);
424 bcm_phy_write_exp(phydev, BCM_EXP_MULTICOLOR, val);
427 bcm54xx_ptp_config_init(phydev);
432 err = bcm_phy_read_exp(phydev, BCM54XX_WOL_INT_STATUS);
437 pm_wakeup_event(&phydev->mdio.dev, 0);
442 static int bcm54xx_iddq_set(struct phy_device *phydev, bool enable)
446 if (!(phydev->dev_flags & PHY_BRCM_IDDQ_SUSPEND))
449 ret = bcm_phy_read_exp(phydev, BCM54XX_TOP_MISC_IDDQ_CTRL);
458 ret = bcm_phy_write_exp(phydev, BCM54XX_TOP_MISC_IDDQ_CTRL, ret);
463 static int bcm54xx_set_wakeup_irq(struct phy_device *phydev, bool state)
465 struct bcm54xx_phy_priv *priv = phydev->priv;
468 if (!bcm54xx_phy_can_wakeup(phydev))
482 static int bcm54xx_suspend(struct phy_device *phydev)
486 bcm54xx_ptp_stop(phydev);
489 ret = bcm_phy_read_exp(phydev, BCM54XX_WOL_INT_STATUS);
493 if (phydev->wol_enabled)
494 return bcm54xx_set_wakeup_irq(phydev, true);
500 ret = phy_write(phydev, MII_BMCR, BMCR_PDOWN);
504 return bcm54xx_iddq_set(phydev, true);
507 static int bcm54xx_resume(struct phy_device *phydev)
511 if (phydev->wol_enabled) {
512 ret = bcm54xx_set_wakeup_irq(phydev, false);
517 ret = bcm54xx_iddq_set(phydev, false);
524 ret = genphy_resume(phydev);
536 if (phydev->dev_flags & PHY_BRCM_IDDQ_SUSPEND) {
537 ret = genphy_soft_reset(phydev);
542 return bcm54xx_config_init(phydev);
545 static int bcm54810_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
550 static int bcm54810_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
556 static int bcm54811_config_init(struct phy_device *phydev)
561 reg = bcm_phy_read_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL);
563 err = bcm_phy_write_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL,
568 err = bcm54xx_config_init(phydev);
571 if (!(phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED)) {
572 reg = bcm_phy_read_exp(phydev, BCM54612E_EXP_SPARE0);
573 err = bcm_phy_write_exp(phydev, BCM54612E_EXP_SPARE0,
582 static int bcm5481_config_aneg(struct phy_device *phydev)
584 struct device_node *np = phydev->mdio.dev.of_node;
588 ret = genphy_config_aneg(phydev);
591 bcm54xx_config_clock_delay(phydev);
595 ret = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_SEL_ER + 0x9,
608 static int bcm54616s_probe(struct phy_device *phydev)
613 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
617 phydev->priv = priv;
619 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE);
630 val = bcm_phy_read_shadow(phydev, BCM54616S_SHD_100FX_CTRL);
642 phydev->port = PORT_FIBRE;
648 static int bcm54616s_config_aneg(struct phy_device *phydev)
650 struct bcm54616s_phy_priv *priv = phydev->priv;
655 ret = genphy_c37_config_aneg(phydev);
657 ret = genphy_config_aneg(phydev);
660 bcm54xx_config_clock_delay(phydev);
665 static int bcm54616s_read_status(struct phy_device *phydev)
667 struct bcm54616s_phy_priv *priv = phydev->priv;
671 err = genphy_c37_read_status(phydev);
673 err = genphy_read_status(phydev);
678 static int brcm_fet_config_init(struct phy_device *phydev)
683 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
703 err = phy_read(phydev, MII_BMCR);
707 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
718 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
723 brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST);
729 err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg);
734 reg = phy_read(phydev, MII_BRCM_FET_SHDW_AUXMODE4);
743 err = phy_write(phydev, MII_BRCM_FET_SHDW_AUXMODE4, reg);
748 err = phy_set_bits(phydev, MII_BRCM_FET_SHDW_MISCCTRL,
753 if (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE) {
755 err = phy_set_bits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2,
761 err2 = phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest);
768 static int brcm_fet_ack_interrupt(struct phy_device *phydev)
773 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
780 static int brcm_fet_config_intr(struct phy_device *phydev)
784 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
788 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
789 err = brcm_fet_ack_interrupt(phydev);
794 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
797 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
801 err = brcm_fet_ack_interrupt(phydev);
807 static irqreturn_t brcm_fet_handle_interrupt(struct phy_device *phydev)
811 irq_status = phy_read(phydev, MII_BRCM_FET_INTREG);
813 phy_error(phydev);
820 phy_trigger_machine(phydev);
825 static int brcm_fet_suspend(struct phy_device *phydev)
832 err = phy_write(phydev, MII_BMCR, BMCR_PDOWN);
837 brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST);
843 err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg);
848 err = phy_modify(phydev, MII_BRCM_FET_SHDW_AUXMODE4,
853 err2 = phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest);
860 static void bcm54xx_phy_get_wol(struct phy_device *phydev,
868 if (!bcm54xx_phy_can_wakeup(phydev)) {
873 bcm_phy_get_wol(phydev, wol);
876 static int bcm54xx_phy_set_wol(struct phy_device *phydev,
886 if (!bcm54xx_phy_can_wakeup(phydev))
889 ret = bcm_phy_set_wol(phydev, wol);
896 static int bcm54xx_phy_probe(struct phy_device *phydev)
902 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
908 phydev->priv = priv;
910 priv->stats = devm_kcalloc(&phydev->mdio.dev,
911 bcm_phy_get_sset_count(phydev), sizeof(u64),
916 priv->ptp = bcm_ptp_probe(phydev);
924 wakeup_gpio = devm_gpiod_get(&phydev->mdio.dev, "wakeup", GPIOD_IN);
934 ret = devm_request_irq(&phydev->mdio.dev, priv->wake_irq,
937 dev_name(&phydev->mdio.dev), phydev);
945 if (!bcm54xx_phy_can_wakeup(phydev))
948 return device_init_wakeup(&phydev->mdio.dev, true);
951 static void bcm54xx_get_stats(struct phy_device *phydev,
954 struct bcm54xx_phy_priv *priv = phydev->priv;
956 bcm_phy_get_stats(phydev, priv->stats, stats, data);
959 static void bcm54xx_link_change_notify(struct phy_device *phydev)
965 if (phydev->state != PHY_RUNNING)
971 if (!(phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
974 ret = bcm_phy_read_exp(phydev, MII_BCM54XX_EXP_EXP08);
982 if (phydev->speed == SPEED_10)
986 bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP08, ret);