Lines Matching defs:phydev
180 static int aqr107_get_sset_count(struct phy_device *phydev)
185 static void aqr107_get_strings(struct phy_device *phydev, u8 *data)
194 static u64 aqr107_get_stat(struct phy_device *phydev, int index)
202 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg);
208 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1);
218 static void aqr107_get_stats(struct phy_device *phydev,
221 struct aqr107_priv *priv = phydev->priv;
226 val = aqr107_get_stat(phydev, i);
228 phydev_err(phydev, "Reading HW Statistics failed for %s\n",
237 static int aqr_config_aneg(struct phy_device *phydev)
243 if (phydev->autoneg == AUTONEG_DISABLE)
244 return genphy_c45_pma_setup_forced(phydev);
246 ret = genphy_c45_an_config_aneg(phydev);
257 phydev->advertising))
261 phydev->advertising))
266 phydev->advertising))
270 phydev->advertising))
273 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
283 return genphy_c45_check_and_restart_aneg(phydev, changed);
286 static int aqr_config_intr(struct phy_device *phydev)
288 bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED;
293 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2);
298 err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2,
303 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK,
308 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK,
316 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2);
324 static irqreturn_t aqr_handle_interrupt(struct phy_device *phydev)
328 irq_status = phy_read_mmd(phydev, MDIO_MMD_AN,
331 phy_error(phydev);
338 phy_trigger_machine(phydev);
343 static int aqr_read_status(struct phy_device *phydev)
347 if (phydev->autoneg == AUTONEG_ENABLE) {
348 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1);
353 phydev->lp_advertising,
356 phydev->lp_advertising,
360 return genphy_c45_read_status(phydev);
363 static int aqr107_read_rate(struct phy_device *phydev)
368 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1);
373 phydev->duplex = DUPLEX_FULL;
375 phydev->duplex = DUPLEX_HALF;
379 phydev->speed = SPEED_10;
383 phydev->speed = SPEED_100;
387 phydev->speed = SPEED_1000;
391 phydev->speed = SPEED_2500;
395 phydev->speed = SPEED_5000;
399 phydev->speed = SPEED_10000;
403 phydev->speed = SPEED_UNKNOWN;
407 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, config_reg);
413 phydev->rate_matching = RATE_MATCH_PAUSE;
415 phydev->rate_matching = RATE_MATCH_NONE;
420 static int aqr107_read_status(struct phy_device *phydev)
424 ret = aqr_read_status(phydev);
428 if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE)
431 val = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_IF_STATUS);
437 phydev->interface = PHY_INTERFACE_MODE_10GKR;
440 phydev->interface = PHY_INTERFACE_MODE_1000BASEKX;
443 phydev->interface = PHY_INTERFACE_MODE_10GBASER;
446 phydev->interface = PHY_INTERFACE_MODE_USXGMII;
449 phydev->interface = PHY_INTERFACE_MODE_XAUI;
452 phydev->interface = PHY_INTERFACE_MODE_SGMII;
455 phydev->interface = PHY_INTERFACE_MODE_RXAUI;
458 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
461 phydev->interface = PHY_INTERFACE_MODE_NA;
466 return aqr107_read_rate(phydev);
469 static int aqr107_get_downshift(struct phy_device *phydev, u8 *data)
473 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV);
485 static int aqr107_set_downshift(struct phy_device *phydev, u8 cnt)
497 return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
502 static int aqr107_get_tunable(struct phy_device *phydev,
507 return aqr107_get_downshift(phydev, data);
513 static int aqr107_set_tunable(struct phy_device *phydev,
518 return aqr107_set_downshift(phydev, *(const u8 *)data);
531 static int aqr107_wait_reset_complete(struct phy_device *phydev)
535 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
540 static void aqr107_chip_info(struct phy_device *phydev)
545 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID);
552 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1);
559 phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n",
563 static int aqr107_config_init(struct phy_device *phydev)
568 if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
569 phydev->interface != PHY_INTERFACE_MODE_1000BASEKX &&
570 phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
571 phydev->interface != PHY_INTERFACE_MODE_XGMII &&
572 phydev->interface != PHY_INTERFACE_MODE_USXGMII &&
573 phydev->interface != PHY_INTERFACE_MODE_10GKR &&
574 phydev->interface != PHY_INTERFACE_MODE_10GBASER &&
575 phydev->interface != PHY_INTERFACE_MODE_XAUI &&
576 phydev->interface != PHY_INTERFACE_MODE_RXAUI)
579 WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII,
582 ret = aqr107_wait_reset_complete(phydev);
584 aqr107_chip_info(phydev);
586 return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
589 static int aqcs109_config_init(struct phy_device *phydev)
594 if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
595 phydev->interface != PHY_INTERFACE_MODE_2500BASEX)
598 ret = aqr107_wait_reset_complete(phydev);
600 aqr107_chip_info(phydev);
606 phy_set_max_speed(phydev, SPEED_2500);
608 return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
611 static void aqr107_link_change_notify(struct phy_device *phydev)
617 if (phydev->state != PHY_RUNNING || phydev->autoneg == AUTONEG_DISABLE)
620 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1);
628 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT4);
635 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_VEND_STAT3);
641 phydev_dbg(phydev, "Link partner is Aquantia PHY, FW %u.%u%s%s%s\n",
647 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9);
653 phydev_info(phydev, "Aquantia 1000Base-T2 mode active\n");
656 static int aqr107_wait_processor_intensive_op(struct phy_device *phydev)
667 err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
673 phydev_err(phydev, "timeout: processor-intensive MDIO operation\n");
680 static int aqr107_get_rate_matching(struct phy_device *phydev,
690 static int aqr107_suspend(struct phy_device *phydev)
694 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
699 return aqr107_wait_processor_intensive_op(phydev);
702 static int aqr107_resume(struct phy_device *phydev)
706 err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
711 return aqr107_wait_processor_intensive_op(phydev);
714 static int aqr107_probe(struct phy_device *phydev)
716 phydev->priv = devm_kzalloc(&phydev->mdio.dev,
718 if (!phydev->priv)
721 return aqr_hwmon_probe(phydev);