Lines Matching refs:ret
72 int ret;
74 ret = genphy_c45_read_status(phydev);
75 if (ret)
76 return ret;
78 ret = phy_read_mmd(phydev, MDIO_MMD_AN, ADIN_AN_PHY_INST_STATUS);
79 if (ret < 0)
80 return ret;
82 if (ret & ADIN_IS_CFG_SLV)
85 if (ret & ADIN_IS_CFG_MST)
94 int ret;
97 ret = genphy_c45_pma_setup_forced(phydev);
98 if (ret < 0)
99 return ret;
102 ret = phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_B10L_PMA_CTRL,
105 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_B10L_PMA_CTRL,
107 if (ret < 0)
108 return ret;
114 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_AN, ADIN_FORCED_MODE, ADIN_FORCED_MODE_EN);
115 if (ret < 0)
116 return ret;
120 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_H,
123 if (ret < 0)
124 return ret;
129 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_H,
132 if (ret < 0)
133 return ret;
141 int ret;
145 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1,
147 if (ret < 0)
148 return ret;
150 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, ADIN_CRSM_STAT, ret,
151 (ret & ADIN_CRSM_SFT_PD_RDY) == val,
178 int ret;
180 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ADIN_CRSM_SFT_RST, ADIN_CRSM_SFT_RST_EN);
181 if (ret < 0)
182 return ret;
184 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, ADIN_CRSM_STAT, ret,
185 (ret & ADIN_CRSM_SYS_RDY),
193 int ret;
196 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10T1L_STAT);
197 if (ret < 0)
198 return ret;
201 priv->tx_level_2v4_able = !!(ret & MDIO_PMA_10T1L_STAT_2V4_ABLE);
208 ret = device_property_read_u8(dev, "phy-10base-t1l-2.4vpp", &val);
209 if (ret < 0)
210 return ret;
228 int ret;
230 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT1);
231 if (ret < 0)
232 return ret;
233 else if (!(ret & MDIO_STAT1_LSTATUS))
236 ret = phy_read_mmd(phydev, MDIO_STAT1, ADIN_MSE_VAL);
237 if (ret < 0)
238 return ret;
240 mse_val = 0xFFFF & ret;