Lines Matching defs:txgbe_write_pma
54 static int txgbe_write_pma(struct dw_xpcs *xpcs, int reg, u16 val)
63 txgbe_write_pma(xpcs, TXGBE_MPLLA_CTL0, 0x21);
64 txgbe_write_pma(xpcs, TXGBE_MPLLA_CTL3, 0);
67 txgbe_write_pma(xpcs, TXGBE_TX_GENCTL1, val);
68 txgbe_write_pma(xpcs, TXGBE_MISC_CTL0, TXGBE_MISC_CTL0_PLL |
70 txgbe_write_pma(xpcs, TXGBE_VCO_CAL_LD0, 0x549);
71 txgbe_write_pma(xpcs, TXGBE_VCO_CAL_REF0, 0x29);
72 txgbe_write_pma(xpcs, TXGBE_TX_RATE_CTL, 0);
73 txgbe_write_pma(xpcs, TXGBE_RX_RATE_CTL, 0);
74 txgbe_write_pma(xpcs, TXGBE_TX_GEN_CTL2, TXGBE_TX_GEN_CTL2_TX0_WIDTH(3));
75 txgbe_write_pma(xpcs, TXGBE_RX_GEN_CTL2, TXGBE_RX_GEN_CTL2_RX0_WIDTH(3));
76 txgbe_write_pma(xpcs, TXGBE_MPLLA_CTL2, TXGBE_MPLLA_CTL2_DIV16P5_CLK_EN |
79 txgbe_write_pma(xpcs, TXGBE_RX_EQ_CTL0, TXGBE_RX_EQ_CTL0_CTLE_POLE(2) |
83 txgbe_write_pma(xpcs, TXGBE_RX_EQ_ATTN_CTL, val);
84 txgbe_write_pma(xpcs, TXGBE_DFE_TAP_CTL0, 0xBE);
87 txgbe_write_pma(xpcs, TXGBE_AFE_DFE_ENABLE, val);
90 txgbe_write_pma(xpcs, TXGBE_RX_EQ_CTL4, val);
100 txgbe_write_pma(xpcs, TXGBE_TX_GENCTL1, val);
101 txgbe_write_pma(xpcs, TXGBE_MISC_CTL0, TXGBE_MISC_CTL0_PLL |
104 txgbe_write_pma(xpcs, TXGBE_RX_EQ_CTL0, TXGBE_RX_EQ_CTL0_VGA1_GAIN(7) |
108 txgbe_write_pma(xpcs, TXGBE_RX_EQ_ATTN_CTL, val);
109 txgbe_write_pma(xpcs, TXGBE_DFE_TAP_CTL0, 0);
112 txgbe_write_pma(xpcs, TXGBE_RX_EQ_ATTN_CTL, val);
114 txgbe_write_pma(xpcs, TXGBE_MPLLA_CTL0, 0x20);
115 txgbe_write_pma(xpcs, TXGBE_MPLLA_CTL3, 0x46);
116 txgbe_write_pma(xpcs, TXGBE_VCO_CAL_LD0, 0x540);
117 txgbe_write_pma(xpcs, TXGBE_VCO_CAL_REF0, 0x2A);
118 txgbe_write_pma(xpcs, TXGBE_AFE_DFE_ENABLE, 0);
119 txgbe_write_pma(xpcs, TXGBE_RX_EQ_CTL4, TXGBE_RX_EQ_CTL4_CONT_OFF_CAN0);
120 txgbe_write_pma(xpcs, TXGBE_TX_RATE_CTL, TXGBE_TX_RATE_CTL_TX0_RATE(3));
121 txgbe_write_pma(xpcs, TXGBE_RX_RATE_CTL, TXGBE_RX_RATE_CTL_RX0_RATE(3));
122 txgbe_write_pma(xpcs, TXGBE_TX_GEN_CTL2, TXGBE_TX_GEN_CTL2_TX0_WIDTH(1));
123 txgbe_write_pma(xpcs, TXGBE_RX_GEN_CTL2, TXGBE_RX_GEN_CTL2_RX0_WIDTH(1));
124 txgbe_write_pma(xpcs, TXGBE_MPLLA_CTL2, TXGBE_MPLLA_CTL2_DIV10_CLK_EN);