Lines Matching refs:membase
41 void __iomem *membase;
51 return readl_poll_timeout(priv->membase + MDIO_CMD_REG, busy,
66 data = readl(priv->membase + MDIO_MODE_REG);
70 writel(data, priv->membase + MDIO_MODE_REG);
73 writel((mii_id << 8) | mmd, priv->membase + MDIO_ADDR_REG);
76 writel(reg, priv->membase + MDIO_DATA_WRITE_REG);
81 writel(cmd, priv->membase + MDIO_CMD_REG);
89 writel(cmd, priv->membase + MDIO_CMD_REG);
95 return readl(priv->membase + MDIO_DATA_READ_REG);
107 data = readl(priv->membase + MDIO_MODE_REG);
111 writel(data, priv->membase + MDIO_MODE_REG);
114 writel((mii_id << 8) | regnum, priv->membase + MDIO_ADDR_REG);
119 writel(cmd, priv->membase + MDIO_CMD_REG);
126 return readl(priv->membase + MDIO_DATA_READ_REG);
139 data = readl(priv->membase + MDIO_MODE_REG);
143 writel(data, priv->membase + MDIO_MODE_REG);
146 writel((mii_id << 8) | mmd, priv->membase + MDIO_ADDR_REG);
149 writel(reg, priv->membase + MDIO_DATA_WRITE_REG);
153 writel(cmd, priv->membase + MDIO_CMD_REG);
159 writel(value, priv->membase + MDIO_DATA_WRITE_REG);
162 writel(cmd, priv->membase + MDIO_CMD_REG);
182 data = readl(priv->membase + MDIO_MODE_REG);
186 writel(data, priv->membase + MDIO_MODE_REG);
189 writel((mii_id << 8) | regnum, priv->membase + MDIO_ADDR_REG);
192 writel(value, priv->membase + MDIO_DATA_WRITE_REG);
197 writel(cmd, priv->membase + MDIO_CMD_REG);
247 priv->membase = devm_platform_ioremap_resource(pdev, 0);
248 if (IS_ERR(priv->membase))
249 return PTR_ERR(priv->membase);