Lines Matching refs:val
455 u32 val;
464 val = ioread32(ipa->reg_virt + offset);
469 state = !!(val & mask);
473 val ^= mask;
474 iowrite32(val, ipa->reg_virt + offset);
497 u32 val;
502 val = ioread32(ipa->reg_virt + reg_n_offset(reg, unit));
504 return !!(val & BIT(endpoint_id % 32));
649 u32 val = 0;
661 val |= reg_encode(reg, CS_METADATA_HDR_OFFSET, off);
674 val |= reg_encode(reg, CS_OFFLOAD_EN, enabled);
677 iowrite32(val, ipa->reg_virt + reg_n_offset(reg, endpoint_id));
685 u32 val;
691 val = reg_encode(reg, NAT_EN, IPA_NAT_TYPE_BYPASS);
693 iowrite32(val, ipa->reg_virt + reg_n_offset(reg, endpoint_id));
722 u32 val;
725 val = reg_encode(reg, HDR_LEN, header_size & field_max);
728 return val;
734 val |= reg_encode(reg, HDR_LEN_MSB, header_size);
736 return val;
744 u32 val;
747 val = reg_encode(reg, HDR_OFST_METADATA, offset);
750 return val;
756 val |= reg_encode(reg, HDR_OFST_METADATA_MSB, offset);
758 return val;
787 u32 val = 0;
795 val = ipa_header_size_encode(version, reg, header_size);
803 val |= ipa_metadata_offset_encode(version, reg, off);
811 val |= reg_bit(reg, HDR_OFST_PKT_SIZE_VALID);
812 val |= reg_encode(reg, HDR_OFST_PKT_SIZE, off);
815 val |= reg_bit(reg, HDR_OFST_METADATA_VALID);
823 iowrite32(val, ipa->reg_virt + reg_n_offset(reg, endpoint_id));
832 u32 val = 0;
837 val |= reg_bit(reg, HDR_ENDIANNESS); /* big endian */
847 val |= reg_bit(reg, HDR_TOTAL_LEN_OR_PAD_VALID);
849 val |= reg_bit(reg, HDR_PAYLOAD_LEN_INC_PADDING);
856 val |= reg_encode(reg, HDR_PAD_TO_ALIGNMENT, pad_align);
870 val |= reg_encode(reg, HDR_OFST_PKT_SIZE_MSB, off);
875 iowrite32(val, ipa->reg_virt + reg_n_offset(reg, endpoint_id));
883 u32 val = 0;
894 val = (__force u32)cpu_to_be32(IPA_ENDPOINT_QMAP_METADATA_MASK);
896 iowrite32(val, ipa->reg_virt + offset);
904 u32 val;
914 val = reg_encode(reg, ENDP_MODE, IPA_DMA);
915 val |= reg_encode(reg, DEST_PIPE_INDEX, dma_endpoint_id);
917 val = reg_encode(reg, ENDP_MODE, IPA_BASIC);
922 iowrite32(val, ipa->reg_virt + offset);
998 u32 val = 0;
1008 val |= reg_encode(reg, AGGR_EN, IPA_ENABLE_AGGR);
1009 val |= reg_encode(reg, AGGR_TYPE, IPA_GENERIC);
1014 val |= reg_encode(reg, BYTE_LIMIT, limit);
1017 val |= aggr_time_limit_encode(ipa, reg, limit);
1022 val |= reg_bit(reg, SW_EOF_ACTIVE);
1024 val |= reg_encode(reg, AGGR_EN, IPA_ENABLE_DEAGGR);
1025 val |= reg_encode(reg, AGGR_TYPE, IPA_QCMAP);
1031 val |= reg_encode(reg, AGGR_EN, IPA_BYPASS_AGGR);
1035 iowrite32(val, ipa->reg_virt + reg_n_offset(reg, endpoint_id));
1054 u32 val;
1100 val = reg_encode(reg, TIMER_SCALE, scale);
1101 val |= reg_encode(reg, TIMER_BASE_VALUE, (u32)ticks >> scale);
1103 return val;
1113 u32 val;
1117 val = hol_block_timer_encode(ipa, reg, microseconds);
1119 iowrite32(val, ipa->reg_virt + reg_n_offset(reg, endpoint_id));
1129 u32 val;
1133 val = enable ? reg_bit(reg, HOL_BLOCK_EN) : 0;
1135 iowrite32(val, ipa->reg_virt + offset);
1139 iowrite32(val, ipa->reg_virt + offset);
1175 u32 val = 0;
1186 iowrite32(val, ipa->reg_virt + reg_n_offset(reg, endpoint_id));
1195 u32 val;
1198 val = reg_encode(reg, ENDP_RSRC_GRP, resource_group);
1200 iowrite32(val, ipa->reg_virt + reg_n_offset(reg, endpoint_id));
1208 u32 val;
1216 val = reg_encode(reg, SEQ_TYPE, endpoint->config.tx.seq_type);
1220 val |= reg_encode(reg, SEQ_REP_TYPE,
1223 iowrite32(val, ipa->reg_virt + reg_n_offset(reg, endpoint_id));
1274 u32 val = 0;
1278 val |= reg_bit(reg, STATUS_EN);
1286 val |= reg_encode(reg, STATUS_ENDP, status_endpoint_id);
1294 iowrite32(val, ipa->reg_virt + reg_n_offset(reg, endpoint_id));
1639 u32 val;
1643 val = reg_encode(reg, ROUTE_DEF_PIPE, endpoint_id);
1644 val |= reg_bit(reg, ROUTE_DEF_HDR_TABLE);
1646 val |= reg_encode(reg, ROUTE_FRAG_DEF_PIPE, endpoint_id);
1647 val |= reg_bit(reg, ROUTE_DEF_RETAIN_HDR);
1649 iowrite32(val, ipa->reg_virt + reg_offset(reg));
1994 u32 val;
2021 val = ioread32(ipa->reg_virt + reg_offset(reg));
2024 tx_count = reg_decode(reg, MAX_CONS_PIPES, val);
2025 rx_count = reg_decode(reg, MAX_PROD_PIPES, val);
2026 rx_base = reg_decode(reg, PROD_LOWEST, val);