Lines Matching refs:reg
244 const struct reg *reg;
305 reg = ipa_reg(ipa, ENDP_INIT_AGGR);
307 limit = reg_field_max(reg, BYTE_LIMIT);
450 const struct reg *reg;
462 reg = ipa_reg(ipa, ENDP_INIT_CTRL);
463 offset = reg_n_offset(reg, endpoint->endpoint_id);
467 mask = reg_bit(reg, field_id);
496 const struct reg *reg;
501 reg = ipa_reg(ipa, STATE_AGGR_ACTIVE);
502 val = ioread32(ipa->reg_virt + reg_n_offset(reg, unit));
513 const struct reg *reg;
517 reg = ipa_reg(ipa, AGGR_FORCE_CLOSE);
518 iowrite32(mask, ipa->reg_virt + reg_n_offset(reg, unit));
616 const struct reg *reg;
624 reg = ipa_reg(ipa, ENDP_STATUS);
625 offset = reg_n_offset(reg, endpoint_id);
648 const struct reg *reg;
651 reg = ipa_reg(ipa, ENDP_INIT_CFG);
661 val |= reg_encode(reg, CS_METADATA_HDR_OFFSET, off);
674 val |= reg_encode(reg, CS_OFFLOAD_EN, enabled);
677 iowrite32(val, ipa->reg_virt + reg_n_offset(reg, endpoint_id));
684 const struct reg *reg;
690 reg = ipa_reg(ipa, ENDP_INIT_NAT);
691 val = reg_encode(reg, NAT_EN, IPA_NAT_TYPE_BYPASS);
693 iowrite32(val, ipa->reg_virt + reg_n_offset(reg, endpoint_id));
719 const struct reg *reg, u32 header_size)
721 u32 field_max = reg_field_max(reg, HDR_LEN);
725 val = reg_encode(reg, HDR_LEN, header_size & field_max);
733 WARN_ON(header_size > reg_field_max(reg, HDR_LEN_MSB));
734 val |= reg_encode(reg, HDR_LEN_MSB, header_size);
741 const struct reg *reg, u32 offset)
743 u32 field_max = reg_field_max(reg, HDR_OFST_METADATA);
747 val = reg_encode(reg, HDR_OFST_METADATA, offset);
755 WARN_ON(offset > reg_field_max(reg, HDR_OFST_METADATA_MSB));
756 val |= reg_encode(reg, HDR_OFST_METADATA_MSB, offset);
786 const struct reg *reg;
789 reg = ipa_reg(ipa, ENDP_INIT_HDR);
795 val = ipa_header_size_encode(version, reg, header_size);
803 val |= ipa_metadata_offset_encode(version, reg, off);
809 off &= reg_field_max(reg, HDR_OFST_PKT_SIZE);
811 val |= reg_bit(reg, HDR_OFST_PKT_SIZE_VALID);
812 val |= reg_encode(reg, HDR_OFST_PKT_SIZE, off);
815 val |= reg_bit(reg, HDR_OFST_METADATA_VALID);
823 iowrite32(val, ipa->reg_virt + reg_n_offset(reg, endpoint_id));
831 const struct reg *reg;
834 reg = ipa_reg(ipa, ENDP_INIT_HDR_EXT);
837 val |= reg_bit(reg, HDR_ENDIANNESS); /* big endian */
847 val |= reg_bit(reg, HDR_TOTAL_LEN_OR_PAD_VALID);
849 val |= reg_bit(reg, HDR_PAYLOAD_LEN_INC_PADDING);
856 val |= reg_encode(reg, HDR_PAD_TO_ALIGNMENT, pad_align);
864 u32 mask = reg_field_max(reg, HDR_OFST_PKT_SIZE);
870 val |= reg_encode(reg, HDR_OFST_PKT_SIZE_MSB, off);
875 iowrite32(val, ipa->reg_virt + reg_n_offset(reg, endpoint_id));
882 const struct reg *reg;
889 reg = ipa_reg(ipa, ENDP_INIT_HDR_METADATA_MASK);
890 offset = reg_n_offset(reg, endpoint_id);
902 const struct reg *reg;
909 reg = ipa_reg(ipa, ENDP_INIT_MODE);
914 val = reg_encode(reg, ENDP_MODE, IPA_DMA);
915 val |= reg_encode(reg, DEST_PIPE_INDEX, dma_endpoint_id);
917 val = reg_encode(reg, ENDP_MODE, IPA_BASIC);
921 offset = reg_n_offset(reg, endpoint->endpoint_id);
966 static u32 aggr_time_limit_encode(struct ipa *ipa, const struct reg *reg,
975 max = reg_field_max(reg, TIME_LIMIT);
981 return reg_encode(reg, AGGR_GRAN_SEL, select) |
982 reg_encode(reg, TIME_LIMIT, ticks);
990 return reg_encode(reg, TIME_LIMIT, ticks);
997 const struct reg *reg;
1000 reg = ipa_reg(ipa, ENDP_INIT_AGGR);
1008 val |= reg_encode(reg, AGGR_EN, IPA_ENABLE_AGGR);
1009 val |= reg_encode(reg, AGGR_TYPE, IPA_GENERIC);
1014 val |= reg_encode(reg, BYTE_LIMIT, limit);
1017 val |= aggr_time_limit_encode(ipa, reg, limit);
1022 val |= reg_bit(reg, SW_EOF_ACTIVE);
1024 val |= reg_encode(reg, AGGR_EN, IPA_ENABLE_DEAGGR);
1025 val |= reg_encode(reg, AGGR_TYPE, IPA_QCMAP);
1031 val |= reg_encode(reg, AGGR_EN, IPA_BYPASS_AGGR);
1035 iowrite32(val, ipa->reg_virt + reg_n_offset(reg, endpoint_id));
1046 static u32 hol_block_timer_encode(struct ipa *ipa, const struct reg *reg,
1060 u32 max = reg_field_max(reg, TIMER_LIMIT);
1066 return reg_encode(reg, TIMER_GRAN_SEL, 1) |
1067 reg_encode(reg, TIMER_LIMIT, ticks);
1075 WARN_ON(ticks > reg_field_max(reg, TIMER_BASE_VALUE));
1079 return reg_encode(reg, TIMER_BASE_VALUE, (u32)ticks);
1090 width = hweight32(reg_fmask(reg, TIMER_BASE_VALUE));
1100 val = reg_encode(reg, TIMER_SCALE, scale);
1101 val |= reg_encode(reg, TIMER_BASE_VALUE, (u32)ticks >> scale);
1112 const struct reg *reg;
1116 reg = ipa_reg(ipa, ENDP_INIT_HOL_BLOCK_TIMER);
1117 val = hol_block_timer_encode(ipa, reg, microseconds);
1119 iowrite32(val, ipa->reg_virt + reg_n_offset(reg, endpoint_id));
1127 const struct reg *reg;
1131 reg = ipa_reg(ipa, ENDP_INIT_HOL_BLOCK_EN);
1132 offset = reg_n_offset(reg, endpoint_id);
1133 val = enable ? reg_bit(reg, HOL_BLOCK_EN) : 0;
1174 const struct reg *reg;
1180 reg = ipa_reg(ipa, ENDP_INIT_DEAGGR);
1186 iowrite32(val, ipa->reg_virt + reg_n_offset(reg, endpoint_id));
1194 const struct reg *reg;
1197 reg = ipa_reg(ipa, ENDP_INIT_RSRC_GRP);
1198 val = reg_encode(reg, ENDP_RSRC_GRP, resource_group);
1200 iowrite32(val, ipa->reg_virt + reg_n_offset(reg, endpoint_id));
1207 const struct reg *reg;
1213 reg = ipa_reg(ipa, ENDP_INIT_SEQ);
1216 val = reg_encode(reg, SEQ_TYPE, endpoint->config.tx.seq_type);
1220 val |= reg_encode(reg, SEQ_REP_TYPE,
1223 iowrite32(val, ipa->reg_virt + reg_n_offset(reg, endpoint_id));
1273 const struct reg *reg;
1276 reg = ipa_reg(ipa, ENDP_STATUS);
1278 val |= reg_bit(reg, STATUS_EN);
1286 val |= reg_encode(reg, STATUS_ENDP, status_endpoint_id);
1294 iowrite32(val, ipa->reg_virt + reg_n_offset(reg, endpoint_id));
1638 const struct reg *reg;
1641 reg = ipa_reg(ipa, ROUTE);
1643 val = reg_encode(reg, ROUTE_DEF_PIPE, endpoint_id);
1644 val |= reg_bit(reg, ROUTE_DEF_HDR_TABLE);
1646 val |= reg_encode(reg, ROUTE_FRAG_DEF_PIPE, endpoint_id);
1647 val |= reg_bit(reg, ROUTE_DEF_RETAIN_HDR);
1649 iowrite32(val, ipa->reg_virt + reg_offset(reg));
1987 const struct reg *reg;
2020 reg = ipa_reg(ipa, FLAVOR_0);
2021 val = ioread32(ipa->reg_virt + reg_offset(reg));
2024 tx_count = reg_decode(reg, MAX_CONS_PIPES, val);
2025 rx_count = reg_decode(reg, MAX_PROD_PIPES, val);
2026 rx_base = reg_decode(reg, PROD_LOWEST, val);