Lines Matching refs:entry
118 * The adapter DMA engine supports a 256 entry receive descriptor block
135 * Like the receive path, the adapter DMA engine supports a 256 entry
2281 * Note: The adapters utilize an on-board 64 entry CAM for
2465 PI_LAN_ADDR *p_addr; /* pointer to CAM entry */
2473 * entry to be two longwords (8 bytes total). We must be
2475 * multicast table entry into each command entry. This
2482 p_addr = &bp->cmd_req_virt->addr_filter_set.entry[0];
2491 p_addr++; /* point to next command entry */
2502 p_addr++; /* point to next command entry */
2987 * buffers in powers of 2 so that we can easily fill the 256 entry descriptor
3109 int entry;
3111 entry = bp->rcv_xmt_reg.index.rcv_comp;
3113 p_buff = (char *) (((struct sk_buff *)bp->p_rcv_buff_va[entry])->data);
3115 p_buff = bp->p_rcv_buff_va[entry];
3117 dma_addr = bp->descr_block_virt->rcv_data[entry].long_1;
3167 skb = (struct sk_buff *)bp->p_rcv_buff_va[entry];
3173 bp->p_rcv_buff_va[entry] = (char *)newskb;
3174 bp->descr_block_virt->rcv_data[entry].long_1 = (u32)new_dma_addr;
3298 PI_XMT_DESCR *p_xmt_descr; /* ptr to transmit descriptor block entry */
3370 * Get pointer to auxiliary queue entry to contain information
3376 * next auxiliary queue entry now before we bump the