Lines Matching defs:PutByte
310 #define PutByte(reg,value) outb((value), ioaddr+(reg))
356 PutByte(XIRCREG2_GPR2, 0x04|0); /* drive MDCK low */
358 PutByte(XIRCREG2_GPR2, 0x04|1); /* and drive MDCK high */
370 PutByte(XIRCREG2_GPR2, 0x0c|2|0); /* set MDIO */
372 PutByte(XIRCREG2_GPR2, 0x0c|2|1); /* and drive MDCK high */
375 PutByte(XIRCREG2_GPR2, 0x0c|0|0); /* clear MDIO */
377 PutByte(XIRCREG2_GPR2, 0x0c|0|1); /* and drive MDCK high */
403 PutByte(XIRCREG2_GPR2, 4|0); /* drive MDCK low */
406 PutByte(XIRCREG2_GPR2, 4|1); /* drive MDCK high again */
992 PutByte(XIRCREG_CR, 0);
1012 PutByte(XIRCREG40_RXST0, (~rx_status & 0xff));
1015 PutByte(XIRCREG40_TXST0, 0);
1016 PutByte(XIRCREG40_TXST1, 0);
1126 PutByte(XIRCREG_CR, ClearRxOvrun);
1147 PutByte(XIRCREG_CR, RestartTx); /* restart transmitter process */
1182 PutByte(XIRCREG_CR, EnableIntr); /* re-enable interrupts */
1185 * PutByte(XIRCREG_CR, EnableIntr|ForceIntr);
1257 PutByte(XIRCREG_EDP, skb->data[pktlen-1]);
1260 PutByte(XIRCREG_CR, TransmitPacket|EnableIntr);
1287 PutByte(sa_info->reg_nr++, addr[5 - i]);
1289 PutByte(sa_info->reg_nr++, addr[i]);
1343 PutByte(XIRCREG42_SWC1, value | 0x06); /* set MPE and PME */
1345 PutByte(XIRCREG42_SWC1, value | 0x02); /* set MPE */
1348 PutByte(XIRCREG42_SWC1, value | 0x01);
1350 PutByte(XIRCREG40_CMD0, Offline);
1353 PutByte(XIRCREG40_CMD0, EnableRecv | Online);
1355 PutByte(XIRCREG42_SWC1, value | 0x00);
1459 PutByte(XIRCREG4_GPR1, 0); /* clear bit 0: power down */
1462 PutByte(XIRCREG4_GPR1, 1); /* set bit 0: power up */
1464 PutByte(XIRCREG4_GPR1, 1 | 4); /* set bit 0: power up, bit 2: AIC */
1478 PutByte(XIRCREG_CR, SoftReset); /* set */
1480 PutByte(XIRCREG_CR, 0); /* clear */
1488 PutByte(XIRCREG4_GPR0, 0x0e);
1501 PutByte(XIRCREG4_GPR0, 4);
1506 PutByte(XIRCREG42_SWC1, 0xC0);
1509 PutByte(XIRCREG42_SWC1, 0x80);
1523 PutByte(XIRCREG1_IMR0, 0xff); /* allow all ints */
1524 PutByte(XIRCREG1_IMR1, 1 ); /* and Set TxUnderrunDetect */
1529 PutByte(XIRCREG1_ECR, value);
1534 PutByte(XIRCREG42_SWC0, 0x20); /* disable source insertion */
1558 PutByte(XIRCREG40_RMASK0, 0xff); /* ROK, RAB, rsv, RO, CRC, AE, PTL, MP */
1559 PutByte(XIRCREG40_TMASK0, 0xff); /* TOK, TAB, SQE, LL, TU, JAB, EXC, CRS */
1560 PutByte(XIRCREG40_TMASK1, 0xb0); /* rsv, rsv, PTD, EXT, rsv,rsv,rsv, rsv*/
1561 PutByte(XIRCREG40_RXST0, 0x00); /* ROK, RAB, REN, RO, CRC, AE, PTL, MP */
1562 PutByte(XIRCREG40_TXST0, 0x00); /* TOK, TAB, SQE, LL, TU, JAB, EXC, CRS */
1563 PutByte(XIRCREG40_TXST1, 0x00); /* TEN, rsv, PTD, EXT, retry_counter:4 */
1569 PutByte(XIRCREG2_MSR, GetByte(XIRCREG2_MSR) | 0x08);
1575 PutByte(XIRCREG42_SWC1, 0xC0);
1577 PutByte(XIRCREG42_SWC1, 0x80);
1581 PutByte(XIRCREG1_ECR, GetByte(XIRCREG1_ECR | FullDuplex));
1591 PutByte(XIRCREG2_LED, 0x3b);
1593 PutByte(XIRCREG2_LED, 0x3a);
1596 PutByte(0x0b, 0x04); /* 100 Mbit LED */
1602 PutByte(XIRCREG40_CMD0, EnableRecv | Online);
1607 PutByte(XIRCREG1_IMR0, 0xff);
1610 PutByte(XIRCREG_CR, EnableIntr);
1613 PutByte(0x10, 0x11); /* unmask master-int bit */
1708 PutByte(XIRCREG4_GPR1, 0); /* clear bit 0: power down */
1727 PutByte(XIRCREG_CR, 0); /* disable interrupts */
1729 PutByte(XIRCREG1_IMR0, 0x00); /* forbid all ints */
1731 PutByte(XIRCREG4_GPR1, 0); /* clear bit 0: power down */