Lines Matching refs:ale
231 static int cpsw_ale_entry_get_fld(struct cpsw_ale *ale,
239 if (!ale || !ale_entry)
244 dev_err(ale->params.dev, "get: wrong ale fld id %d\n", fld_id);
250 bits = ale->port_mask_bits;
255 static void cpsw_ale_entry_set_fld(struct cpsw_ale *ale,
264 if (!ale || !ale_entry)
269 dev_err(ale->params.dev, "set: wrong ale fld id %d\n", fld_id);
275 bits = ale->port_mask_bits;
280 static int cpsw_ale_vlan_get_fld(struct cpsw_ale *ale,
284 return cpsw_ale_entry_get_fld(ale, ale_entry,
285 ale->vlan_entry_tbl, fld_id);
288 static void cpsw_ale_vlan_set_fld(struct cpsw_ale *ale,
293 cpsw_ale_entry_set_fld(ale, ale_entry,
294 ale->vlan_entry_tbl, fld_id, value);
314 static int cpsw_ale_read(struct cpsw_ale *ale, int idx, u32 *ale_entry)
318 WARN_ON(idx > ale->params.ale_entries);
320 writel_relaxed(idx, ale->params.ale_regs + ALE_TABLE_CONTROL);
323 ale_entry[i] = readl_relaxed(ale->params.ale_regs +
329 static int cpsw_ale_write(struct cpsw_ale *ale, int idx, u32 *ale_entry)
333 WARN_ON(idx > ale->params.ale_entries);
336 writel_relaxed(ale_entry[i], ale->params.ale_regs +
339 writel_relaxed(idx | ALE_TABLE_WRITE, ale->params.ale_regs +
345 static int cpsw_ale_match_addr(struct cpsw_ale *ale, const u8 *addr, u16 vid)
350 for (idx = 0; idx < ale->params.ale_entries; idx++) {
353 cpsw_ale_read(ale, idx, ale_entry);
366 static int cpsw_ale_match_vlan(struct cpsw_ale *ale, u16 vid)
371 for (idx = 0; idx < ale->params.ale_entries; idx++) {
372 cpsw_ale_read(ale, idx, ale_entry);
382 static int cpsw_ale_match_free(struct cpsw_ale *ale)
387 for (idx = 0; idx < ale->params.ale_entries; idx++) {
388 cpsw_ale_read(ale, idx, ale_entry);
396 static int cpsw_ale_find_ageable(struct cpsw_ale *ale)
401 for (idx = 0; idx < ale->params.ale_entries; idx++) {
402 cpsw_ale_read(ale, idx, ale_entry);
416 static void cpsw_ale_flush_mcast(struct cpsw_ale *ale, u32 *ale_entry,
422 ale->port_mask_bits);
430 ale->port_mask_bits);
435 int cpsw_ale_flush_multicast(struct cpsw_ale *ale, int port_mask, int vid)
440 for (idx = 0; idx < ale->params.ale_entries; idx++) {
441 cpsw_ale_read(ale, idx, ale_entry);
462 cpsw_ale_flush_mcast(ale, ale_entry, port_mask);
465 cpsw_ale_write(ale, idx, ale_entry);
481 int cpsw_ale_add_ucast(struct cpsw_ale *ale, const u8 *addr, int port,
493 cpsw_ale_set_port_num(ale_entry, port, ale->port_num_bits);
495 idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0);
497 idx = cpsw_ale_match_free(ale);
499 idx = cpsw_ale_find_ageable(ale);
503 cpsw_ale_write(ale, idx, ale_entry);
507 int cpsw_ale_del_ucast(struct cpsw_ale *ale, const u8 *addr, int port,
513 idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0);
518 cpsw_ale_write(ale, idx, ale_entry);
522 int cpsw_ale_add_mcast(struct cpsw_ale *ale, const u8 *addr, int port_mask,
528 idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0);
530 cpsw_ale_read(ale, idx, ale_entry);
539 ale->port_mask_bits);
542 ale->port_mask_bits);
545 idx = cpsw_ale_match_free(ale);
547 idx = cpsw_ale_find_ageable(ale);
551 cpsw_ale_write(ale, idx, ale_entry);
555 int cpsw_ale_del_mcast(struct cpsw_ale *ale, const u8 *addr, int port_mask,
562 idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0);
566 cpsw_ale_read(ale, idx, ale_entry);
570 ale->port_mask_bits);
576 ale->port_mask_bits);
580 cpsw_ale_write(ale, idx, ale_entry);
585 static void cpsw_ale_set_vlan_mcast(struct cpsw_ale *ale, u32 *ale_entry,
591 idx = cpsw_ale_vlan_get_fld(ale, ale_entry,
593 writel(reg_mcast, ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx));
596 idx = cpsw_ale_vlan_get_fld(ale, ale_entry,
598 writel(unreg_mcast, ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx));
601 static void cpsw_ale_set_vlan_untag(struct cpsw_ale *ale, u32 *ale_entry,
604 cpsw_ale_vlan_set_fld(ale, ale_entry,
608 bitmap_set(ale->p0_untag_vid_mask, vid, 1);
610 bitmap_clear(ale->p0_untag_vid_mask, vid, 1);
613 int cpsw_ale_add_vlan(struct cpsw_ale *ale, u16 vid, int port_mask, int untag,
619 idx = cpsw_ale_match_vlan(ale, vid);
621 cpsw_ale_read(ale, idx, ale_entry);
625 cpsw_ale_set_vlan_untag(ale, ale_entry, vid, untag);
627 if (!ale->params.nu_switch_ale) {
628 cpsw_ale_vlan_set_fld(ale, ale_entry,
630 cpsw_ale_vlan_set_fld(ale, ale_entry,
633 cpsw_ale_vlan_set_fld(ale, ale_entry,
636 cpsw_ale_set_vlan_mcast(ale, ale_entry, reg_mcast, unreg_mcast);
639 cpsw_ale_vlan_set_fld(ale, ale_entry,
643 idx = cpsw_ale_match_free(ale);
645 idx = cpsw_ale_find_ageable(ale);
649 cpsw_ale_write(ale, idx, ale_entry);
653 static void cpsw_ale_vlan_del_modify_int(struct cpsw_ale *ale, u32 *ale_entry,
659 members = cpsw_ale_vlan_get_fld(ale, ale_entry,
663 cpsw_ale_set_vlan_untag(ale, ale_entry, vid, 0);
668 untag = cpsw_ale_vlan_get_fld(ale, ale_entry,
670 reg_mcast = cpsw_ale_vlan_get_fld(ale, ale_entry,
672 unreg_mcast = cpsw_ale_vlan_get_fld(ale, ale_entry,
678 cpsw_ale_set_vlan_untag(ale, ale_entry, vid, untag);
680 if (!ale->params.nu_switch_ale) {
681 cpsw_ale_vlan_set_fld(ale, ale_entry,
683 cpsw_ale_vlan_set_fld(ale, ale_entry,
686 cpsw_ale_set_vlan_mcast(ale, ale_entry, reg_mcast,
689 cpsw_ale_vlan_set_fld(ale, ale_entry,
693 int cpsw_ale_vlan_del_modify(struct cpsw_ale *ale, u16 vid, int port_mask)
698 idx = cpsw_ale_match_vlan(ale, vid);
702 cpsw_ale_read(ale, idx, ale_entry);
704 cpsw_ale_vlan_del_modify_int(ale, ale_entry, vid, port_mask);
705 cpsw_ale_write(ale, idx, ale_entry);
710 int cpsw_ale_del_vlan(struct cpsw_ale *ale, u16 vid, int port_mask)
715 idx = cpsw_ale_match_vlan(ale, vid);
719 cpsw_ale_read(ale, idx, ale_entry);
727 members = cpsw_ale_vlan_get_fld(ale, ale_entry, ALE_ENT_VID_MEMBER_LIST);
732 cpsw_ale_set_vlan_untag(ale, ale_entry, vid, 0);
736 cpsw_ale_vlan_del_modify_int(ale, ale_entry, vid, port_mask);
739 cpsw_ale_write(ale, idx, ale_entry);
744 int cpsw_ale_vlan_add_modify(struct cpsw_ale *ale, u16 vid, int port_mask,
752 idx = cpsw_ale_match_vlan(ale, vid);
754 cpsw_ale_read(ale, idx, ale_entry);
756 vlan_members = cpsw_ale_vlan_get_fld(ale, ale_entry,
758 reg_mcast_members = cpsw_ale_vlan_get_fld(ale, ale_entry,
761 cpsw_ale_vlan_get_fld(ale, ale_entry,
763 untag_members = cpsw_ale_vlan_get_fld(ale, ale_entry,
771 ret = cpsw_ale_add_vlan(ale, vid, vlan_members, untag_members,
774 dev_err(ale->params.dev, "Unable to add vlan\n");
777 dev_dbg(ale->params.dev, "port mask 0x%x untag 0x%x\n", vlan_members,
783 void cpsw_ale_set_unreg_mcast(struct cpsw_ale *ale, int unreg_mcast_mask,
790 for (idx = 0; idx < ale->params.ale_entries; idx++) {
791 cpsw_ale_read(ale, idx, ale_entry);
797 cpsw_ale_vlan_get_fld(ale, ale_entry,
803 cpsw_ale_vlan_set_fld(ale, ale_entry,
806 cpsw_ale_write(ale, idx, ale_entry);
810 static void cpsw_ale_vlan_set_unreg_mcast(struct cpsw_ale *ale, u32 *ale_entry,
815 unreg_mcast = cpsw_ale_vlan_get_fld(ale, ale_entry,
822 cpsw_ale_vlan_set_fld(ale, ale_entry,
827 cpsw_ale_vlan_set_unreg_mcast_idx(struct cpsw_ale *ale, u32 *ale_entry,
833 idx = cpsw_ale_vlan_get_fld(ale, ale_entry,
836 unreg_mcast = readl(ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx));
843 writel(unreg_mcast, ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx));
846 void cpsw_ale_set_allmulti(struct cpsw_ale *ale, int allmulti, int port)
851 for (idx = 0; idx < ale->params.ale_entries; idx++) {
854 cpsw_ale_read(ale, idx, ale_entry);
859 vlan_members = cpsw_ale_vlan_get_fld(ale, ale_entry,
865 if (!ale->params.nu_switch_ale)
866 cpsw_ale_vlan_set_unreg_mcast(ale, ale_entry, allmulti);
868 cpsw_ale_vlan_set_unreg_mcast_idx(ale, ale_entry,
871 cpsw_ale_write(ale, idx, ale_entry);
1101 int cpsw_ale_control_set(struct cpsw_ale *ale, int port, int control,
1115 if (port < 0 || port >= ale->params.ale_ports)
1125 tmp = readl_relaxed(ale->params.ale_regs + offset);
1127 writel_relaxed(tmp, ale->params.ale_regs + offset);
1132 int cpsw_ale_control_get(struct cpsw_ale *ale, int port, int control)
1145 if (port < 0 || port >= ale->params.ale_ports)
1151 tmp = readl_relaxed(ale->params.ale_regs + offset) >> shift;
1155 int cpsw_ale_rx_ratelimit_mc(struct cpsw_ale *ale, int port, unsigned int ratelimit_pps)
1162 dev_err(ale->params.dev, "ALE MC port:%d ratelimit min value 1000pps\n", port);
1167 dev_info(ale->params.dev, "ALE port:%d MC ratelimit set to %dpps (requested %d)\n",
1170 cpsw_ale_control_set(ale, port, ALE_PORT_MCAST_LIMIT, val);
1172 dev_dbg(ale->params.dev, "ALE port:%d MC ratelimit set %d\n",
1177 int cpsw_ale_rx_ratelimit_bc(struct cpsw_ale *ale, int port, unsigned int ratelimit_pps)
1184 dev_err(ale->params.dev, "ALE port:%d BC ratelimit min value 1000pps\n", port);
1189 dev_info(ale->params.dev, "ALE port:%d BC ratelimit set to %dpps (requested %d)\n",
1192 cpsw_ale_control_set(ale, port, ALE_PORT_BCAST_LIMIT, val);
1194 dev_dbg(ale->params.dev, "ALE port:%d BC ratelimit set %d\n",
1201 struct cpsw_ale *ale = from_timer(ale, t, timer);
1203 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
1205 if (ale->ageout) {
1206 ale->timer.expires = jiffies + ale->ageout;
1207 add_timer(&ale->timer);
1211 static void cpsw_ale_hw_aging_timer_start(struct cpsw_ale *ale)
1215 aging_timer = ale->params.bus_freq / 1000000;
1216 aging_timer *= ale->params.ale_ageout;
1220 dev_warn(ale->params.dev,
1224 writel(aging_timer, ale->params.ale_regs + ALE_AGING_TIMER);
1227 static void cpsw_ale_hw_aging_timer_stop(struct cpsw_ale *ale)
1229 writel(0, ale->params.ale_regs + ALE_AGING_TIMER);
1232 static void cpsw_ale_aging_start(struct cpsw_ale *ale)
1234 if (!ale->params.ale_ageout)
1237 if (ale->features & CPSW_ALE_F_HW_AUTOAGING) {
1238 cpsw_ale_hw_aging_timer_start(ale);
1242 timer_setup(&ale->timer, cpsw_ale_timer, 0);
1243 ale->timer.expires = jiffies + ale->ageout;
1244 add_timer(&ale->timer);
1247 static void cpsw_ale_aging_stop(struct cpsw_ale *ale)
1249 if (!ale->params.ale_ageout)
1252 if (ale->features & CPSW_ALE_F_HW_AUTOAGING) {
1253 cpsw_ale_hw_aging_timer_stop(ale);
1257 del_timer_sync(&ale->timer);
1260 void cpsw_ale_start(struct cpsw_ale *ale)
1274 ale_prescale = ale->params.bus_freq / ALE_RATE_LIMIT_MIN_PPS;
1275 writel((u32)ale_prescale, ale->params.ale_regs + ALE_PRESCALE);
1280 cpsw_ale_control_set(ale, 0, ALE_RATE_LIMIT, 1);
1282 cpsw_ale_control_set(ale, 0, ALE_ENABLE, 1);
1283 cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1);
1285 cpsw_ale_aging_start(ale);
1288 void cpsw_ale_stop(struct cpsw_ale *ale)
1290 cpsw_ale_aging_stop(ale);
1291 cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1);
1292 cpsw_ale_control_set(ale, 0, ALE_ENABLE, 0);
1367 struct cpsw_ale *ale;
1378 ale = devm_kzalloc(params->dev, sizeof(*ale), GFP_KERNEL);
1379 if (!ale)
1382 ale->p0_untag_vid_mask = devm_bitmap_zalloc(params->dev, VLAN_N_VID,
1384 if (!ale->p0_untag_vid_mask)
1387 ale->params = *params;
1388 ale->ageout = ale->params.ale_ageout * HZ;
1389 ale->features = ale_dev_id->features;
1390 ale->vlan_entry_tbl = ale_dev_id->vlan_entry_tbl;
1392 rev = readl_relaxed(ale->params.ale_regs + ALE_IDVER);
1393 ale->version =
1394 (ALE_VERSION_MAJOR(rev, ale->params.major_ver_mask) << 8) |
1396 dev_info(ale->params.dev, "initialized cpsw ale version %d.%d\n",
1397 ALE_VERSION_MAJOR(rev, ale->params.major_ver_mask),
1400 if (ale->features & CPSW_ALE_F_STATUS_REG &&
1401 !ale->params.ale_entries) {
1403 readl_relaxed(ale->params.ale_regs + ALE_STATUS) &
1416 ale->params.ale_entries = ale_entries;
1418 dev_info(ale->params.dev,
1419 "ALE Table size %ld\n", ale->params.ale_entries);
1422 ale->port_mask_bits = ale->params.ale_ports;
1423 ale->port_num_bits = order_base_2(ale->params.ale_ports);
1424 ale->vlan_field_bits = ale->params.ale_ports;
1429 if (ale->params.nu_switch_ale) {
1431 * Also there are N bits, where N is number of ale
1435 ale->params.ale_ports;
1439 ale->params.ale_ports;
1444 ale->params.ale_ports;
1449 ale->params.ale_ports;
1455 cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1);
1456 return ale;
1459 void cpsw_ale_dump(struct cpsw_ale *ale, u32 *data)
1463 for (i = 0; i < ale->params.ale_entries; i++) {
1464 cpsw_ale_read(ale, i, data);
1469 void cpsw_ale_restore(struct cpsw_ale *ale, u32 *data)
1473 for (i = 0; i < ale->params.ale_entries; i++) {
1474 cpsw_ale_write(ale, i, data);
1479 u32 cpsw_ale_get_num_entries(struct cpsw_ale *ale)
1481 return ale ? ale->params.ale_entries : 0;