Lines Matching defs:port
150 static void am65_cpsw_sl_ctl_reset(struct am65_cpsw_port *port)
152 cpsw_sl_reset(port->slave.mac_sl, 100);
155 port->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN);
174 struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
188 port_mask = BIT(port->port_id) | ALE_PORT_HOST;
203 struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
218 BIT(port->port_id) | ALE_PORT_HOST);
224 static void am65_cpsw_slave_set_promisc(struct am65_cpsw_port *port,
227 struct am65_cpsw_common *common = port->common;
236 cpsw_ale_control_set(common->ale, port->port_id,
241 cpsw_ale_control_set(common->ale, port->port_id,
250 struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
255 am65_cpsw_slave_set_promisc(port, promisc);
262 ndev->flags & IFF_ALLMULTI, port->port_id);
367 static void am65_cpsw_init_port_switch_ale(struct am65_cpsw_port *port);
368 static void am65_cpsw_init_port_emac_ale(struct am65_cpsw_port *port);
398 struct am65_cpsw_port *port = &common->ports[port_idx];
400 if (!port->disabled)
401 val |= BIT(port->port_id);
539 struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
542 phylink_stop(port->slave.phylink);
546 phylink_disconnect_phy(port->slave.phylink);
559 struct am65_cpsw_port *port = arg;
564 return am65_cpsw_nuss_ndo_slave_add_vid(port->ndev, 0, vid);
570 struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
578 /* Idle MAC port */
579 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE);
580 cpsw_sl_wait_for_idle(port->slave.mac_sl, 100);
581 cpsw_sl_ctl_reset(port->slave.mac_sl);
584 cpsw_sl_reg_write(port->slave.mac_sl, CPSW_SL_SOFT_RESET, 1);
586 reg = cpsw_sl_reg_read(port->slave.mac_sl, CPSW_SL_SOFT_RESET);
619 am65_cpsw_port_set_sl_mac(port, ndev->dev_addr);
622 am65_cpsw_init_port_emac_ale(port);
624 am65_cpsw_init_port_switch_ale(port);
627 am65_cpsw_sl_ctl_reset(port);
629 ret = phylink_of_phy_connect(port->slave.phylink, port->slave.phy_node, 0);
634 vlan_for_each(ndev, cpsw_restore_vlans, port);
636 phylink_start(port->slave.phylink);
726 struct am65_cpsw_port *port;
757 port = am65_common_get_port(common, port_id);
758 ndev = port->ndev;
763 if (port->rx_ts_enabled)
1078 struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
1092 if (port->tx_ts_enabled)
1122 cppi5_desc_set_tags_ids(&first_desc->hdr, 0, port->port_id);
1241 struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
1258 am65_cpsw_port_set_sl_mac(port, addr);
1270 struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
1291 port->rx_ts_enabled = false;
1308 port->rx_ts_enabled = true;
1315 port->tx_ts_enabled = (cfg.tx_type == HWTSTAMP_TX_ON);
1336 if (port->tx_ts_enabled)
1340 writel(seq_id, port->port_base + AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG);
1341 writel(ts_vlan_ltype, port->port_base +
1343 writel(ts_ctrl_ltype2, port->port_base +
1345 writel(ts_ctrl, port->port_base + AM65_CPSW_PORTN_REG_TS_CTL);
1348 am65_cpts_rx_enable(common->cpts, port->rx_ts_enabled);
1356 struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
1363 cfg.tx_type = port->tx_ts_enabled ?
1365 cfg.rx_filter = port->rx_ts_enabled ?
1374 struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
1386 return phylink_mii_ioctl(port->slave.phylink, req, cmd);
1464 struct am65_cpsw_port *port;
1469 port = &common->ports[i];
1470 phy = port->slave.serdes_phy;
1477 struct am65_cpsw_port *port)
1488 port->slave.serdes_phy = phy;
1506 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave);
1507 struct am65_cpsw_common *common = port->common;
1512 port->sgmii_base + AM65_CPSW_SGMII_MR_ADV_ABILITY_REG);
1513 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_EXT_EN);
1515 cpsw_sl_ctl_clr(port->slave.mac_sl, CPSW_SL_CTL_EXT_EN);
1519 cpsw_sl_ctl_set(port->slave.mac_sl,
1522 cpsw_sl_ctl_clr(port->slave.mac_sl,
1527 port->sgmii_base + AM65_CPSW_SGMII_CONTROL_REG);
1536 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave);
1537 struct am65_cpsw_common *common = port->common;
1538 struct net_device *ndev = port->ndev;
1543 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1545 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE);
1547 tmo = cpsw_sl_wait_for_idle(port->slave.mac_sl, 100);
1549 cpsw_sl_reg_read(port->slave.mac_sl, CPSW_SL_MACSTATUS), tmo);
1558 cpsw_sl_ctl_clr(port->slave.mac_sl, mac_control);
1570 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave);
1571 struct am65_cpsw_common *common = port->common;
1573 struct net_device *ndev = port->ndev;
1575 /* Bring the port out of idle state */
1576 cpsw_sl_ctl_clr(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE);
1596 cpsw_sl_ctl_set(port->slave.mac_sl, mac_control);
1599 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1611 static void am65_cpsw_nuss_slave_disable_unused(struct am65_cpsw_port *port)
1613 struct am65_cpsw_common *common = port->common;
1615 if (!port->disabled)
1618 cpsw_ale_control_set(common->ale, port->port_id,
1621 cpsw_sl_reset(port->slave.mac_sl, 100);
1622 cpsw_sl_ctl_reset(port->slave.mac_sl);
2015 struct am65_cpsw_port *port;
2018 /* it is not a slave port node, continue */
2019 if (strcmp(port_np->name, "port"))
2036 port = am65_common_get_port(common, port_id);
2037 port->port_id = port_id;
2038 port->common = common;
2039 port->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE +
2042 port->sgmii_base = common->ss_base + AM65_CPSW_SGMII_BASE * (port_id);
2043 port->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE +
2045 port->name = of_get_property(port_np, "label", NULL);
2046 port->fetch_ram_base =
2050 port->slave.mac_sl = cpsw_sl_get("am65", dev, port->port_base);
2051 if (IS_ERR(port->slave.mac_sl)) {
2052 ret = PTR_ERR(port->slave.mac_sl);
2056 port->disabled = !of_device_is_available(port_np);
2057 if (port->disabled) {
2058 common->disabled_ports_mask |= BIT(port->port_id);
2062 port->slave.ifphy = devm_of_phy_get(dev, port_np, NULL);
2063 if (IS_ERR(port->slave.ifphy)) {
2064 ret = PTR_ERR(port->slave.ifphy);
2065 dev_err(dev, "%pOF error retrieving port phy: %d\n",
2070 /* Initialize the Serdes PHY for the port */
2071 ret = am65_cpsw_init_serdes_phy(dev, port_np, port);
2075 port->slave.mac_only =
2079 port->slave.phy_node = port_np;
2080 ret = of_get_phy_mode(port_np, &port->slave.phy_if);
2087 ret = phy_set_mode_ext(port->slave.ifphy, PHY_MODE_ETHERNET, port->slave.phy_if);
2091 ret = of_get_mac_address(port_np, port->slave.mac_addr);
2094 port->port_id,
2095 port->slave.mac_addr);
2096 if (!is_valid_ether_addr(port->slave.mac_addr)) {
2097 eth_random_addr(port->slave.mac_addr);
2104 /* is there at least one ext.port */
2106 dev_err(dev, "No Ext. port are available\n");
2127 struct am65_cpsw_port *port;
2131 port = &common->ports[i];
2132 if (port->slave.phylink)
2133 phylink_destroy(port->slave.phylink);
2142 struct am65_cpsw_port *port;
2146 port = &common->ports[port_idx];
2148 if (port->disabled)
2152 port->ndev = devm_alloc_etherdev_mqs(common->dev,
2156 if (!port->ndev) {
2158 port->port_id);
2162 ndev_priv = netdev_priv(port->ndev);
2163 ndev_priv->port = port;
2165 SET_NETDEV_DEV(port->ndev, dev);
2167 eth_hw_addr_set(port->ndev, port->slave.mac_addr);
2169 port->ndev->min_mtu = AM65_CPSW_MIN_PACKET_SIZE;
2170 port->ndev->max_mtu = AM65_CPSW_MAX_PACKET_SIZE -
2172 port->ndev->hw_features = NETIF_F_SG |
2176 port->ndev->features = port->ndev->hw_features |
2178 port->ndev->vlan_features |= NETIF_F_SG;
2179 port->ndev->netdev_ops = &am65_cpsw_nuss_netdev_ops;
2180 port->ndev->ethtool_ops = &am65_cpsw_ethtool_ops_slave;
2183 port->slave.phylink_config.dev = &port->ndev->dev;
2184 port->slave.phylink_config.type = PHYLINK_NETDEV;
2185 port->slave.phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
2187 port->slave.phylink_config.mac_managed_pm = true; /* MAC does PM */
2189 switch (port->slave.phy_if) {
2194 phy_interface_set_rgmii(port->slave.phylink_config.supported_interfaces);
2199 port->slave.phylink_config.supported_interfaces);
2205 if (common->pdata.extra_modes & BIT(port->slave.phy_if)) {
2206 __set_bit(port->slave.phy_if,
2207 port->slave.phylink_config.supported_interfaces);
2219 phylink = phylink_create(&port->slave.phylink_config,
2220 of_node_to_fwnode(port->slave.phy_node),
2221 port->slave.phy_if,
2226 port->slave.phylink = phylink;
2230 port->ndev->features &= ~NETIF_F_HW_CSUM;
2242 common->dma_ndev = port->ndev;
2263 struct am65_cpsw_port *port;
2267 port = &common->ports[i];
2268 if (port->ndev && port->ndev->reg_state == NETREG_REGISTERED)
2269 unregister_netdev(port->ndev);
2284 struct am65_cpsw_port *port = am65_common_get_port(common, i);
2287 if (!port->ndev)
2290 priv = am65_ndev_to_priv(port->ndev);
2317 /* This is adding the port to a second bridge, this is
2329 common->br_members |= BIT(priv->port->port_id);
2343 common->br_members &= ~BIT(priv->port->port_id);
2465 static void am65_cpsw_init_port_emac_ale(struct am65_cpsw_port *port)
2467 struct am65_cpsw_slave_data *slave = &port->slave;
2468 struct am65_cpsw_common *common = port->common;
2471 writel(slave->port_vlan, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET);
2474 /* enable mac-only mode on port */
2475 cpsw_ale_control_set(common->ale, port->port_id,
2478 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_NOLEARN, 1);
2480 port_mask = BIT(port->port_id) | ALE_PORT_HOST;
2482 cpsw_ale_add_ucast(common->ale, port->ndev->dev_addr,
2484 cpsw_ale_add_mcast(common->ale, port->ndev->broadcast,
2488 static void am65_cpsw_init_port_switch_ale(struct am65_cpsw_port *port)
2490 struct am65_cpsw_slave_data *slave = &port->slave;
2491 struct am65_cpsw_common *cpsw = port->common;
2494 cpsw_ale_control_set(cpsw->ale, port->port_id,
2497 cpsw_ale_add_ucast(cpsw->ale, port->ndev->dev_addr,
2501 port_mask = BIT(port->port_id) | ALE_PORT_HOST;
2503 cpsw_ale_add_mcast(cpsw->ale, port->ndev->broadcast,
2507 writel(slave->port_vlan, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET);
2509 cpsw_ale_control_set(cpsw->ale, port->port_id,
2580 struct am65_cpsw_port *port;
2585 port = am65_ndev_to_port(sl_ndev);
2590 am65_cpsw_init_port_switch_ale(port);
2600 struct am65_cpsw_port *port;
2605 port = am65_ndev_to_port(sl_ndev);
2606 port->slave.port_vlan = 0;
2608 am65_cpsw_init_port_emac_ale(port);
2632 struct am65_cpsw_port *port;
2659 port = am65_common_get_port(common, i);
2660 dl_port = &port->devlink_port;
2662 if (port->ndev)
2666 attrs.phys.port_number = port->port_id;
2671 ret = devlink_port_register(common->devlink, dl_port, port->port_id);
2673 dev_err(dev, "devlink_port reg fail for port %d, ret:%d\n",
2674 port->port_id, ret);
2683 port = am65_common_get_port(common, i);
2684 dl_port = &port->devlink_port;
2696 struct am65_cpsw_port *port;
2702 port = am65_common_get_port(common, i);
2703 dl_port = &port->devlink_port;
2720 struct am65_cpsw_port *port;
2736 port = &common->ports[i];
2738 if (!port->ndev)
2741 SET_NETDEV_DEVLINK_PORT(port->ndev, &port->devlink_port);
2743 ret = register_netdev(port->ndev);
3038 struct am65_cpsw_port *port;
3045 port = &common->ports[i];
3046 ndev = port->ndev;
3051 port->vid_context = readl(port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET);
3075 struct am65_cpsw_port *port;
3094 port = &common->ports[i];
3095 ndev = port->ndev;
3111 writel(port->vid_context, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET);