Lines Matching refs:wptr
171 f->wptr = 0;
1101 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr);
1109 f->m.wptr += sizeof(struct rxf_desc);
1110 delta = f->m.wptr - f->m.memsz;
1112 f->m.wptr = delta;
1120 /*TBD: to do - delayed rxf wptr like in txd */
1121 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1156 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr);
1164 f->m.wptr += sizeof(struct rxf_desc);
1165 delta = f->m.wptr - f->m.memsz;
1167 f->m.wptr = delta;
1208 f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_WR_PTR;
1210 size = f->m.wptr - f->m.rptr;
1371 *pptr != db->wptr); /* or write pointer */
1387 BDX_ASSERT(db->rptr == db->wptr); /* can't read from empty db */
1397 __bdx_tx_db_ptr_next(db, &db->wptr);
1398 BDX_ASSERT(db->rptr == db->wptr); /* we can not get empty db as
1420 * avoid rptr == wptr which means db is empty
1427 d->wptr = d->start;
1476 db->wptr->len = skb_headlen(skb);
1477 db->wptr->addr.dma = dma_map_single(&priv->pdev->dev, skb->data,
1478 db->wptr->len, DMA_TO_DEVICE);
1479 pbl->len = CPU_CHIP_SWAP32(db->wptr->len);
1480 pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(db->wptr->addr.dma));
1481 pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(db->wptr->addr.dma));
1491 db->wptr->len = skb_frag_size(frag);
1492 db->wptr->addr.dma = skb_frag_dma_map(&priv->pdev->dev, frag,
1497 pbl->len = CPU_CHIP_SWAP32(db->wptr->len);
1498 pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(db->wptr->addr.dma));
1499 pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(db->wptr->addr.dma));
1504 db->wptr->len = -txd_sizes[nr_frags].bytes;
1505 db->wptr->addr.skb = skb;
1568 fsize = f->m.rptr - f->m.wptr;
1605 BDX_ASSERT(f->m.wptr >= f->m.memsz); /* started with valid wptr */
1606 txdd = (struct txd_desc *)(f->m.va + f->m.wptr);
1638 f->m.wptr += txd_sizes[nr_frags].bytes;
1639 len = f->m.wptr - f->m.memsz;
1641 f->m.wptr = len;
1647 BDX_ASSERT(f->m.wptr >= f->m.memsz); /* finished with valid wptr */
1657 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1662 f->m.wptr & TXF_WPTR_WR_PTR);
1670 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1703 f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_MASK;
1706 while (f->m.wptr != f->m.rptr) {
1727 BDX_ASSERT((f->m.wptr & TXF_WPTR_WR_PTR) >= f->m.memsz);
1739 priv->txd_fifo0.m.wptr & TXF_WPTR_WR_PTR);
1764 while (db->rptr != db->wptr) {
1799 int i = f->m.memsz - f->m.wptr;
1805 memcpy(f->m.va + f->m.wptr, data, size);
1806 f->m.wptr += size;
1808 memcpy(f->m.va + f->m.wptr, data, i);
1809 f->m.wptr = size - i;
1810 memcpy(f->m.va, data + i, f->m.wptr);
1812 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1830 /* we substruct 8 because when fifo is full rptr == wptr