Lines Matching refs:pdata
36 static int xlgmac_disable_rx_csum(struct xlgmac_pdata *pdata)
40 regval = readl(pdata->mac_regs + MAC_RCR);
43 writel(regval, pdata->mac_regs + MAC_RCR);
48 static int xlgmac_enable_rx_csum(struct xlgmac_pdata *pdata)
52 regval = readl(pdata->mac_regs + MAC_RCR);
55 writel(regval, pdata->mac_regs + MAC_RCR);
60 static int xlgmac_set_mac_address(struct xlgmac_pdata *pdata, const u8 *addr)
68 writel(mac_addr_hi, pdata->mac_regs + MAC_MACA0HR);
69 writel(mac_addr_lo, pdata->mac_regs + MAC_MACA0LR);
74 static void xlgmac_set_mac_reg(struct xlgmac_pdata *pdata,
94 netif_dbg(pdata, drv, pdata->netdev,
104 writel(mac_addr_hi, pdata->mac_regs + *mac_reg);
106 writel(mac_addr_lo, pdata->mac_regs + *mac_reg);
110 static int xlgmac_enable_rx_vlan_stripping(struct xlgmac_pdata *pdata)
114 regval = readl(pdata->mac_regs + MAC_VLANTR);
130 writel(regval, pdata->mac_regs + MAC_VLANTR);
135 static int xlgmac_disable_rx_vlan_stripping(struct xlgmac_pdata *pdata)
139 regval = readl(pdata->mac_regs + MAC_VLANTR);
142 writel(regval, pdata->mac_regs + MAC_VLANTR);
147 static int xlgmac_enable_rx_vlan_filtering(struct xlgmac_pdata *pdata)
151 regval = readl(pdata->mac_regs + MAC_PFR);
155 writel(regval, pdata->mac_regs + MAC_PFR);
157 regval = readl(pdata->mac_regs + MAC_VLANTR);
175 writel(regval, pdata->mac_regs + MAC_VLANTR);
180 static int xlgmac_disable_rx_vlan_filtering(struct xlgmac_pdata *pdata)
184 regval = readl(pdata->mac_regs + MAC_PFR);
188 writel(regval, pdata->mac_regs + MAC_PFR);
217 static int xlgmac_update_vlan_hash_table(struct xlgmac_pdata *pdata)
226 for_each_set_bit(vid, pdata->active_vlans, VLAN_N_VID) {
234 regval = readl(pdata->mac_regs + MAC_VLANHTR);
238 writel(regval, pdata->mac_regs + MAC_VLANHTR);
243 static int xlgmac_set_promiscuous_mode(struct xlgmac_pdata *pdata,
249 regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_PFR),
254 netif_dbg(pdata, drv, pdata->netdev, "%s promiscuous mode\n",
257 regval = readl(pdata->mac_regs + MAC_PFR);
260 writel(regval, pdata->mac_regs + MAC_PFR);
264 xlgmac_disable_rx_vlan_filtering(pdata);
266 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER)
267 xlgmac_enable_rx_vlan_filtering(pdata);
273 static int xlgmac_set_all_multicast_mode(struct xlgmac_pdata *pdata,
279 regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_PFR),
284 netif_dbg(pdata, drv, pdata->netdev, "%s allmulti mode\n",
287 regval = readl(pdata->mac_regs + MAC_PFR);
290 writel(regval, pdata->mac_regs + MAC_PFR);
295 static void xlgmac_set_mac_addn_addrs(struct xlgmac_pdata *pdata)
297 struct net_device *netdev = pdata->netdev;
303 addn_macs = pdata->hw_feat.addn_mac;
306 xlgmac_set_promiscuous_mode(pdata, 1);
309 xlgmac_set_mac_reg(pdata, ha, &mac_reg);
314 xlgmac_set_all_multicast_mode(pdata, 1);
317 xlgmac_set_mac_reg(pdata, ha, &mac_reg);
325 xlgmac_set_mac_reg(pdata, NULL, &mac_reg);
328 static void xlgmac_set_mac_hash_table(struct xlgmac_pdata *pdata)
332 struct net_device *netdev = pdata->netdev;
338 hash_table_shift = 26 - (pdata->hw_feat.hash_table_size >> 7);
339 hash_table_count = pdata->hw_feat.hash_table_size / 32;
358 writel(hash_table[i], pdata->mac_regs + hash_reg);
363 static int xlgmac_add_mac_addresses(struct xlgmac_pdata *pdata)
365 if (pdata->hw_feat.hash_table_size)
366 xlgmac_set_mac_hash_table(pdata);
368 xlgmac_set_mac_addn_addrs(pdata);
373 static void xlgmac_config_mac_address(struct xlgmac_pdata *pdata)
377 xlgmac_set_mac_address(pdata, pdata->netdev->dev_addr);
380 if (pdata->hw_feat.hash_table_size) {
381 regval = readl(pdata->mac_regs + MAC_PFR);
388 writel(regval, pdata->mac_regs + MAC_PFR);
392 static void xlgmac_config_jumbo_enable(struct xlgmac_pdata *pdata)
397 val = (pdata->netdev->mtu > XLGMAC_STD_PACKET_MTU) ? 1 : 0;
399 regval = readl(pdata->mac_regs + MAC_RCR);
402 writel(regval, pdata->mac_regs + MAC_RCR);
405 static void xlgmac_config_checksum_offload(struct xlgmac_pdata *pdata)
407 if (pdata->netdev->features & NETIF_F_RXCSUM)
408 xlgmac_enable_rx_csum(pdata);
410 xlgmac_disable_rx_csum(pdata);
413 static void xlgmac_config_vlan_support(struct xlgmac_pdata *pdata)
417 regval = readl(pdata->mac_regs + MAC_VLANIR);
423 writel(regval, pdata->mac_regs + MAC_VLANIR);
426 xlgmac_update_vlan_hash_table(pdata);
428 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER)
429 xlgmac_enable_rx_vlan_filtering(pdata);
431 xlgmac_disable_rx_vlan_filtering(pdata);
433 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
434 xlgmac_enable_rx_vlan_stripping(pdata);
436 xlgmac_disable_rx_vlan_stripping(pdata);
439 static int xlgmac_config_rx_mode(struct xlgmac_pdata *pdata)
441 struct net_device *netdev = pdata->netdev;
447 xlgmac_set_promiscuous_mode(pdata, pr_mode);
448 xlgmac_set_all_multicast_mode(pdata, am_mode);
450 xlgmac_add_mac_addresses(pdata);
455 static void xlgmac_prepare_tx_stop(struct xlgmac_pdata *pdata,
481 tx_status = readl(pdata->mac_regs + tx_dsr);
492 netdev_info(pdata->netdev,
497 static void xlgmac_enable_tx(struct xlgmac_pdata *pdata)
504 channel = pdata->channel_head;
505 for (i = 0; i < pdata->channel_count; i++, channel++) {
516 for (i = 0; i < pdata->tx_q_count; i++) {
517 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));
521 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));
525 regval = readl(pdata->mac_regs + MAC_TCR);
528 writel(regval, pdata->mac_regs + MAC_TCR);
531 static void xlgmac_disable_tx(struct xlgmac_pdata *pdata)
538 channel = pdata->channel_head;
539 for (i = 0; i < pdata->channel_count; i++, channel++) {
543 xlgmac_prepare_tx_stop(pdata, channel);
547 regval = readl(pdata->mac_regs + MAC_TCR);
550 writel(regval, pdata->mac_regs + MAC_TCR);
553 for (i = 0; i < pdata->tx_q_count; i++) {
554 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));
557 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));
561 channel = pdata->channel_head;
562 for (i = 0; i < pdata->channel_count; i++, channel++) {
573 static void xlgmac_prepare_rx_stop(struct xlgmac_pdata *pdata,
585 rx_status = readl(XLGMAC_MTL_REG(pdata, queue, MTL_Q_RQDR));
597 netdev_info(pdata->netdev,
602 static void xlgmac_enable_rx(struct xlgmac_pdata *pdata)
608 channel = pdata->channel_head;
609 for (i = 0; i < pdata->channel_count; i++, channel++) {
621 for (i = 0; i < pdata->rx_q_count; i++)
623 writel(regval, pdata->mac_regs + MAC_RQC0R);
626 regval = readl(pdata->mac_regs + MAC_RCR);
635 writel(regval, pdata->mac_regs + MAC_RCR);
638 static void xlgmac_disable_rx(struct xlgmac_pdata *pdata)
645 regval = readl(pdata->mac_regs + MAC_RCR);
654 writel(regval, pdata->mac_regs + MAC_RCR);
657 for (i = 0; i < pdata->rx_q_count; i++)
658 xlgmac_prepare_rx_stop(pdata, i);
661 writel(0, pdata->mac_regs + MAC_RQC0R);
664 channel = pdata->channel_head;
665 for (i = 0; i < pdata->channel_count; i++, channel++) {
679 struct xlgmac_pdata *pdata = channel->pdata;
693 if (pdata->tx_usecs && !channel->tx_timer_active) {
696 jiffies + usecs_to_jiffies(pdata->tx_usecs));
704 struct xlgmac_pdata *pdata = channel->pdata;
748 if (!pdata->tx_frames)
750 else if (pkt_info->tx_packets > pdata->tx_frames)
752 else if ((ring->coalesce_count % pdata->tx_frames) <
764 netif_dbg(pdata, tx_queued, pdata->netdev,
793 netif_dbg(pdata, tx_queued, pdata->netdev,
844 pdata->stats.tx_vlan_packets++;
896 pdata->stats.tx_tso_packets++;
990 if (netif_msg_tx_queued(pdata))
991 xlgmac_dump_tx_desc(pdata, ring, start_index,
999 netif_xmit_stopped(netdev_get_tx_queue(pdata->netdev,
1082 static void xlgmac_rx_desc_reset(struct xlgmac_pdata *pdata,
1087 unsigned int rx_frames = pdata->rx_frames;
1088 unsigned int rx_usecs = pdata->rx_usecs;
1141 struct xlgmac_pdata *pdata = channel->pdata;
1152 xlgmac_rx_desc_reset(pdata, desc_data, i);
1188 static int xlgmac_disable_tx_flow_control(struct xlgmac_pdata *pdata)
1195 for (i = 0; i < pdata->rx_q_count; i++) {
1196 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
1199 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
1204 q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count);
1207 regval = readl(pdata->mac_regs + reg);
1212 writel(regval, pdata->mac_regs + reg);
1220 static int xlgmac_enable_tx_flow_control(struct xlgmac_pdata *pdata)
1227 for (i = 0; i < pdata->rx_q_count; i++) {
1228 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
1231 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
1236 q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count);
1239 regval = readl(pdata->mac_regs + reg);
1248 writel(regval, pdata->mac_regs + reg);
1256 static int xlgmac_disable_rx_flow_control(struct xlgmac_pdata *pdata)
1260 regval = readl(pdata->mac_regs + MAC_RFCR);
1263 writel(regval, pdata->mac_regs + MAC_RFCR);
1268 static int xlgmac_enable_rx_flow_control(struct xlgmac_pdata *pdata)
1272 regval = readl(pdata->mac_regs + MAC_RFCR);
1275 writel(regval, pdata->mac_regs + MAC_RFCR);
1280 static int xlgmac_config_tx_flow_control(struct xlgmac_pdata *pdata)
1282 if (pdata->tx_pause)
1283 xlgmac_enable_tx_flow_control(pdata);
1285 xlgmac_disable_tx_flow_control(pdata);
1290 static int xlgmac_config_rx_flow_control(struct xlgmac_pdata *pdata)
1292 if (pdata->rx_pause)
1293 xlgmac_enable_rx_flow_control(pdata);
1295 xlgmac_disable_rx_flow_control(pdata);
1300 static int xlgmac_config_rx_coalesce(struct xlgmac_pdata *pdata)
1306 channel = pdata->channel_head;
1307 for (i = 0; i < pdata->channel_count; i++, channel++) {
1314 pdata->rx_riwt);
1321 static void xlgmac_config_flow_control(struct xlgmac_pdata *pdata)
1323 xlgmac_config_tx_flow_control(pdata);
1324 xlgmac_config_rx_flow_control(pdata);
1327 static void xlgmac_config_rx_fep_enable(struct xlgmac_pdata *pdata)
1332 for (i = 0; i < pdata->rx_q_count; i++) {
1333 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
1336 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
1340 static void xlgmac_config_rx_fup_enable(struct xlgmac_pdata *pdata)
1345 for (i = 0; i < pdata->rx_q_count; i++) {
1346 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
1349 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
1353 static int xlgmac_config_tx_coalesce(struct xlgmac_pdata *pdata)
1358 static void xlgmac_config_rx_buffer_size(struct xlgmac_pdata *pdata)
1364 channel = pdata->channel_head;
1365 for (i = 0; i < pdata->channel_count; i++, channel++) {
1372 pdata->rx_buf_size);
1377 static void xlgmac_config_tso_mode(struct xlgmac_pdata *pdata)
1383 channel = pdata->channel_head;
1384 for (i = 0; i < pdata->channel_count; i++, channel++) {
1388 if (pdata->hw_feat.tso) {
1397 static void xlgmac_config_sph_mode(struct xlgmac_pdata *pdata)
1403 channel = pdata->channel_head;
1404 for (i = 0; i < pdata->channel_count; i++, channel++) {
1414 regval = readl(pdata->mac_regs + MAC_RCR);
1418 writel(regval, pdata->mac_regs + MAC_RCR);
1421 static unsigned int xlgmac_usec_to_riwt(struct xlgmac_pdata *pdata,
1427 rate = pdata->sysclk_rate;
1439 static unsigned int xlgmac_riwt_to_usec(struct xlgmac_pdata *pdata,
1445 rate = pdata->sysclk_rate;
1457 static int xlgmac_config_rx_threshold(struct xlgmac_pdata *pdata,
1463 for (i = 0; i < pdata->rx_q_count; i++) {
1464 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
1467 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
1473 static void xlgmac_config_mtl_mode(struct xlgmac_pdata *pdata)
1479 regval = readl(pdata->mac_regs + MTL_OMR);
1482 writel(regval, pdata->mac_regs + MTL_OMR);
1485 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) {
1486 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_TC_ETSCR));
1489 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_TC_ETSCR));
1491 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_TC_QWR));
1494 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_TC_QWR));
1498 regval = readl(pdata->mac_regs + MTL_OMR);
1501 writel(regval, pdata->mac_regs + MTL_OMR);
1504 static void xlgmac_config_queue_mapping(struct xlgmac_pdata *pdata)
1515 qptc = pdata->tx_q_count / pdata->hw_feat.tc_cnt;
1516 qptc_extra = pdata->tx_q_count % pdata->hw_feat.tc_cnt;
1518 for (i = 0, queue = 0; i < pdata->hw_feat.tc_cnt; i++) {
1520 netif_dbg(pdata, drv, pdata->netdev,
1522 regval = readl(XLGMAC_MTL_REG(pdata, queue,
1528 writel(regval, XLGMAC_MTL_REG(pdata, queue,
1534 netif_dbg(pdata, drv, pdata->netdev,
1536 regval = readl(XLGMAC_MTL_REG(pdata, queue,
1542 writel(regval, XLGMAC_MTL_REG(pdata, queue,
1550 pdata->rx_q_count);
1559 netif_dbg(pdata, drv, pdata->netdev,
1566 netif_dbg(pdata, drv, pdata->netdev,
1577 writel(regval, pdata->mac_regs + reg);
1586 regval = readl(pdata->mac_regs + reg);
1589 writel(regval, pdata->mac_regs + reg);
1592 regval = readl(pdata->mac_regs + reg);
1595 writel(regval, pdata->mac_regs + reg);
1598 regval = readl(pdata->mac_regs + reg);
1601 writel(regval, pdata->mac_regs + reg);
1630 static void xlgmac_config_tx_fifo_size(struct xlgmac_pdata *pdata)
1637 pdata->hw_feat.tx_fifo_size,
1638 pdata->tx_q_count);
1640 for (i = 0; i < pdata->tx_q_count; i++) {
1641 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));
1644 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));
1647 netif_info(pdata, drv, pdata->netdev,
1649 pdata->tx_q_count, ((fifo_size + 1) * 256));
1652 static void xlgmac_config_rx_fifo_size(struct xlgmac_pdata *pdata)
1659 pdata->hw_feat.rx_fifo_size,
1660 pdata->rx_q_count);
1662 for (i = 0; i < pdata->rx_q_count; i++) {
1663 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
1666 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
1669 netif_info(pdata, drv, pdata->netdev,
1671 pdata->rx_q_count, ((fifo_size + 1) * 256));
1674 static void xlgmac_config_flow_control_threshold(struct xlgmac_pdata *pdata)
1679 for (i = 0; i < pdata->rx_q_count; i++) {
1680 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQFCR));
1687 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQFCR));
1691 static int xlgmac_config_tx_threshold(struct xlgmac_pdata *pdata,
1697 for (i = 0; i < pdata->tx_q_count; i++) {
1698 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));
1701 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));
1707 static int xlgmac_config_rsf_mode(struct xlgmac_pdata *pdata,
1713 for (i = 0; i < pdata->rx_q_count; i++) {
1714 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
1717 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR));
1723 static int xlgmac_config_tsf_mode(struct xlgmac_pdata *pdata,
1729 for (i = 0; i < pdata->tx_q_count; i++) {
1730 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));
1733 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));
1739 static int xlgmac_config_osp_mode(struct xlgmac_pdata *pdata)
1745 channel = pdata->channel_head;
1746 for (i = 0; i < pdata->channel_count; i++, channel++) {
1753 pdata->tx_osp_mode);
1760 static int xlgmac_config_pblx8(struct xlgmac_pdata *pdata)
1766 channel = pdata->channel_head;
1767 for (i = 0; i < pdata->channel_count; i++, channel++) {
1771 pdata->pblx8);
1778 static int xlgmac_get_tx_pbl_val(struct xlgmac_pdata *pdata)
1782 regval = readl(XLGMAC_DMA_REG(pdata->channel_head, DMA_CH_TCR));
1788 static int xlgmac_config_tx_pbl_val(struct xlgmac_pdata *pdata)
1794 channel = pdata->channel_head;
1795 for (i = 0; i < pdata->channel_count; i++, channel++) {
1802 pdata->tx_pbl);
1809 static int xlgmac_get_rx_pbl_val(struct xlgmac_pdata *pdata)
1813 regval = readl(XLGMAC_DMA_REG(pdata->channel_head, DMA_CH_RCR));
1819 static int xlgmac_config_rx_pbl_val(struct xlgmac_pdata *pdata)
1825 channel = pdata->channel_head;
1826 for (i = 0; i < pdata->channel_count; i++, channel++) {
1833 pdata->rx_pbl);
1840 static u64 xlgmac_mmc_read(struct xlgmac_pdata *pdata, unsigned int reg_lo)
1858 val = (u64)readl(pdata->mac_regs + reg_lo);
1861 val |= ((u64)readl(pdata->mac_regs + reg_lo + 4) << 32);
1866 static void xlgmac_tx_mmc_int(struct xlgmac_pdata *pdata)
1868 unsigned int mmc_isr = readl(pdata->mac_regs + MMC_TISR);
1869 struct xlgmac_stats *stats = &pdata->stats;
1875 xlgmac_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO);
1881 xlgmac_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO);
1887 xlgmac_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO);
1893 xlgmac_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO);
1899 xlgmac_mmc_read(pdata, MMC_TX64OCTETS_GB_LO);
1905 xlgmac_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO);
1911 xlgmac_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO);
1917 xlgmac_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO);
1923 xlgmac_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO);
1929 xlgmac_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO);
1935 xlgmac_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO);
1941 xlgmac_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO);
1947 xlgmac_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO);
1953 xlgmac_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO);
1959 xlgmac_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO);
1965 xlgmac_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO);
1971 xlgmac_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO);
1977 xlgmac_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO);
1980 static void xlgmac_rx_mmc_int(struct xlgmac_pdata *pdata)
1982 unsigned int mmc_isr = readl(pdata->mac_regs + MMC_RISR);
1983 struct xlgmac_stats *stats = &pdata->stats;
1989 xlgmac_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO);
1995 xlgmac_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO);
2001 xlgmac_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO);
2007 xlgmac_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO);
2013 xlgmac_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO);
2019 xlgmac_mmc_read(pdata, MMC_RXCRCERROR_LO);
2025 xlgmac_mmc_read(pdata, MMC_RXRUNTERROR);
2031 xlgmac_mmc_read(pdata, MMC_RXJABBERERROR);
2037 xlgmac_mmc_read(pdata, MMC_RXUNDERSIZE_G);
2043 xlgmac_mmc_read(pdata, MMC_RXOVERSIZE_G);
2049 xlgmac_mmc_read(pdata, MMC_RX64OCTETS_GB_LO);
2055 xlgmac_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO);
2061 xlgmac_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO);
2067 xlgmac_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO);
2073 xlgmac_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO);
2079 xlgmac_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO);
2085 xlgmac_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO);
2091 xlgmac_mmc_read(pdata, MMC_RXLENGTHERROR_LO);
2097 xlgmac_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO);
2103 xlgmac_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO);
2109 xlgmac_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO);
2115 xlgmac_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO);
2121 xlgmac_mmc_read(pdata, MMC_RXWATCHDOGERROR);
2124 static void xlgmac_read_mmc_stats(struct xlgmac_pdata *pdata)
2126 struct xlgmac_stats *stats = &pdata->stats;
2130 regval = readl(pdata->mac_regs + MMC_CR);
2133 writel(regval, pdata->mac_regs + MMC_CR);
2136 xlgmac_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO);
2139 xlgmac_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO);
2142 xlgmac_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO);
2145 xlgmac_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO);
2148 xlgmac_mmc_read(pdata, MMC_TX64OCTETS_GB_LO);
2151 xlgmac_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO);
2154 xlgmac_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO);
2157 xlgmac_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO);
2160 xlgmac_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO);
2163 xlgmac_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO);
2166 xlgmac_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO);
2169 xlgmac_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO);
2172 xlgmac_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO);
2175 xlgmac_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO);
2178 xlgmac_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO);
2181 xlgmac_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO);
2184 xlgmac_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO);
2187 xlgmac_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO);
2190 xlgmac_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO);
2193 xlgmac_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO);
2196 xlgmac_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO);
2199 xlgmac_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO);
2202 xlgmac_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO);
2205 xlgmac_mmc_read(pdata, MMC_RXCRCERROR_LO);
2208 xlgmac_mmc_read(pdata, MMC_RXRUNTERROR);
2211 xlgmac_mmc_read(pdata, MMC_RXJABBERERROR);
2214 xlgmac_mmc_read(pdata, MMC_RXUNDERSIZE_G);
2217 xlgmac_mmc_read(pdata, MMC_RXOVERSIZE_G);
2220 xlgmac_mmc_read(pdata, MMC_RX64OCTETS_GB_LO);
2223 xlgmac_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO);
2226 xlgmac_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO);
2229 xlgmac_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO);
2232 xlgmac_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO);
2235 xlgmac_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO);
2238 xlgmac_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO);
2241 xlgmac_mmc_read(pdata, MMC_RXLENGTHERROR_LO);
2244 xlgmac_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO);
2247 xlgmac_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO);
2250 xlgmac_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO);
2253 xlgmac_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO);
2256 xlgmac_mmc_read(pdata, MMC_RXWATCHDOGERROR);
2259 regval = readl(pdata->mac_regs + MMC_CR);
2262 writel(regval, pdata->mac_regs + MMC_CR);
2265 static void xlgmac_config_mmc(struct xlgmac_pdata *pdata)
2269 regval = readl(pdata->mac_regs + MMC_CR);
2276 writel(regval, pdata->mac_regs + MMC_CR);
2279 static int xlgmac_write_rss_reg(struct xlgmac_pdata *pdata, unsigned int type,
2286 mutex_lock(&pdata->rss_mutex);
2288 regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_RSSAR),
2295 writel(val, pdata->mac_regs + MAC_RSSDR);
2297 regval = readl(pdata->mac_regs + MAC_RSSAR);
2306 writel(regval, pdata->mac_regs + MAC_RSSAR);
2310 regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_RSSAR),
2322 mutex_unlock(&pdata->rss_mutex);
2327 static int xlgmac_write_rss_hash_key(struct xlgmac_pdata *pdata)
2329 unsigned int key_regs = sizeof(pdata->rss_key) / sizeof(u32);
2330 unsigned int *key = (unsigned int *)&pdata->rss_key;
2334 ret = xlgmac_write_rss_reg(pdata, XLGMAC_RSS_HASH_KEY_TYPE,
2343 static int xlgmac_write_rss_lookup_table(struct xlgmac_pdata *pdata)
2348 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) {
2349 ret = xlgmac_write_rss_reg(pdata,
2351 pdata->rss_table[i]);
2359 static int xlgmac_set_rss_hash_key(struct xlgmac_pdata *pdata, const u8 *key)
2361 memcpy(pdata->rss_key, key, sizeof(pdata->rss_key));
2363 return xlgmac_write_rss_hash_key(pdata);
2366 static int xlgmac_set_rss_lookup_table(struct xlgmac_pdata *pdata,
2372 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) {
2374 pdata->rss_table[i] = XLGMAC_SET_REG_BITS(
2375 pdata->rss_table[i],
2381 return xlgmac_write_rss_lookup_table(pdata);
2384 static int xlgmac_enable_rss(struct xlgmac_pdata *pdata)
2389 if (!pdata->hw_feat.rss)
2393 ret = xlgmac_write_rss_hash_key(pdata);
2398 ret = xlgmac_write_rss_lookup_table(pdata);
2403 writel(pdata->rss_options, pdata->mac_regs + MAC_RSSCR);
2406 regval = readl(pdata->mac_regs + MAC_RSSCR);
2409 writel(regval, pdata->mac_regs + MAC_RSSCR);
2414 static int xlgmac_disable_rss(struct xlgmac_pdata *pdata)
2418 if (!pdata->hw_feat.rss)
2421 regval = readl(pdata->mac_regs + MAC_RSSCR);
2424 writel(regval, pdata->mac_regs + MAC_RSSCR);
2429 static void xlgmac_config_rss(struct xlgmac_pdata *pdata)
2433 if (!pdata->hw_feat.rss)
2436 if (pdata->netdev->features & NETIF_F_RXHASH)
2437 ret = xlgmac_enable_rss(pdata);
2439 ret = xlgmac_disable_rss(pdata);
2442 netdev_err(pdata->netdev,
2446 static void xlgmac_enable_dma_interrupts(struct xlgmac_pdata *pdata)
2452 channel = pdata->channel_head;
2453 for (i = 0; i < pdata->channel_count; i++, channel++) {
2481 if (!pdata->per_channel_irq)
2499 if (!pdata->per_channel_irq)
2511 static void xlgmac_enable_mtl_interrupts(struct xlgmac_pdata *pdata)
2516 q_count = max(pdata->hw_feat.tx_q_cnt, pdata->hw_feat.rx_q_cnt);
2519 mtl_q_isr = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_ISR));
2520 writel(mtl_q_isr, XLGMAC_MTL_REG(pdata, i, MTL_Q_ISR));
2523 writel(0, XLGMAC_MTL_REG(pdata, i, MTL_Q_IER));
2527 static void xlgmac_enable_mac_interrupts(struct xlgmac_pdata *pdata)
2536 writel(mac_ier, pdata->mac_regs + MAC_IER);
2539 regval = readl(pdata->mac_regs + MMC_RIER);
2542 writel(regval, pdata->mac_regs + MMC_RIER);
2543 regval = readl(pdata->mac_regs + MMC_TIER);
2546 writel(regval, pdata->mac_regs + MMC_TIER);
2549 static int xlgmac_set_xlgmii_25000_speed(struct xlgmac_pdata *pdata)
2553 regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_TCR),
2558 regval = readl(pdata->mac_regs + MAC_TCR);
2561 writel(regval, pdata->mac_regs + MAC_TCR);
2566 static int xlgmac_set_xlgmii_40000_speed(struct xlgmac_pdata *pdata)
2570 regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_TCR),
2575 regval = readl(pdata->mac_regs + MAC_TCR);
2578 writel(regval, pdata->mac_regs + MAC_TCR);
2583 static int xlgmac_set_xlgmii_50000_speed(struct xlgmac_pdata *pdata)
2587 regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_TCR),
2592 regval = readl(pdata->mac_regs + MAC_TCR);
2595 writel(regval, pdata->mac_regs + MAC_TCR);
2600 static int xlgmac_set_xlgmii_100000_speed(struct xlgmac_pdata *pdata)
2604 regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_TCR),
2609 regval = readl(pdata->mac_regs + MAC_TCR);
2612 writel(regval, pdata->mac_regs + MAC_TCR);
2617 static void xlgmac_config_mac_speed(struct xlgmac_pdata *pdata)
2619 switch (pdata->phy_speed) {
2621 xlgmac_set_xlgmii_100000_speed(pdata);
2625 xlgmac_set_xlgmii_50000_speed(pdata);
2629 xlgmac_set_xlgmii_40000_speed(pdata);
2633 xlgmac_set_xlgmii_25000_speed(pdata);
2640 struct xlgmac_pdata *pdata = channel->pdata;
2642 struct net_device *netdev = pdata->netdev;
2661 if (netif_msg_rx_status(pdata))
2662 xlgmac_dump_rx_desc(pdata, ring, ring->cur);
2708 pdata->stats.rx_split_header_packets++;
2777 netif_dbg(pdata, rx_status, netdev, "err=%u, etlt=%#x\n", err, etlt);
2792 netif_dbg(pdata, rx_status, netdev, "vlan-ctag=%#06x\n",
2943 static int xlgmac_flush_tx_queues(struct xlgmac_pdata *pdata)
2948 for (i = 0; i < pdata->tx_q_count; i++) {
2949 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));
2952 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));
2956 for (i = 0; i < pdata->tx_q_count; i++) {
2958 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR));
2971 static void xlgmac_config_dma_bus(struct xlgmac_pdata *pdata)
2975 regval = readl(pdata->mac_regs + DMA_SBMR);
2984 writel(regval, pdata->mac_regs + DMA_SBMR);
2987 static int xlgmac_hw_init(struct xlgmac_pdata *pdata)
2989 struct xlgmac_desc_ops *desc_ops = &pdata->desc_ops;
2993 ret = xlgmac_flush_tx_queues(pdata);
2998 xlgmac_config_dma_bus(pdata);
2999 xlgmac_config_osp_mode(pdata);
3000 xlgmac_config_pblx8(pdata);
3001 xlgmac_config_tx_pbl_val(pdata);
3002 xlgmac_config_rx_pbl_val(pdata);
3003 xlgmac_config_rx_coalesce(pdata);
3004 xlgmac_config_tx_coalesce(pdata);
3005 xlgmac_config_rx_buffer_size(pdata);
3006 xlgmac_config_tso_mode(pdata);
3007 xlgmac_config_sph_mode(pdata);
3008 xlgmac_config_rss(pdata);
3009 desc_ops->tx_desc_init(pdata);
3010 desc_ops->rx_desc_init(pdata);
3011 xlgmac_enable_dma_interrupts(pdata);
3014 xlgmac_config_mtl_mode(pdata);
3015 xlgmac_config_queue_mapping(pdata);
3016 xlgmac_config_tsf_mode(pdata, pdata->tx_sf_mode);
3017 xlgmac_config_rsf_mode(pdata, pdata->rx_sf_mode);
3018 xlgmac_config_tx_threshold(pdata, pdata->tx_threshold);
3019 xlgmac_config_rx_threshold(pdata, pdata->rx_threshold);
3020 xlgmac_config_tx_fifo_size(pdata);
3021 xlgmac_config_rx_fifo_size(pdata);
3022 xlgmac_config_flow_control_threshold(pdata);
3023 xlgmac_config_rx_fep_enable(pdata);
3024 xlgmac_config_rx_fup_enable(pdata);
3025 xlgmac_enable_mtl_interrupts(pdata);
3028 xlgmac_config_mac_address(pdata);
3029 xlgmac_config_rx_mode(pdata);
3030 xlgmac_config_jumbo_enable(pdata);
3031 xlgmac_config_flow_control(pdata);
3032 xlgmac_config_mac_speed(pdata);
3033 xlgmac_config_checksum_offload(pdata);
3034 xlgmac_config_vlan_support(pdata);
3035 xlgmac_config_mmc(pdata);
3036 xlgmac_enable_mac_interrupts(pdata);
3041 static int xlgmac_hw_exit(struct xlgmac_pdata *pdata)
3047 regval = readl(pdata->mac_regs + DMA_MR);
3050 writel(regval, pdata->mac_regs + DMA_MR);
3055 XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + DMA_MR),