Lines Matching defs:channel
456 struct xlgmac_channel *channel)
463 if (channel->queue_index < DMA_DSRX_FIRST_QUEUE) {
465 tx_pos = (channel->queue_index * DMA_DSR_Q_LEN) +
468 tx_qidx = channel->queue_index - DMA_DSRX_FIRST_QUEUE;
493 "timed out waiting for Tx DMA channel %u to stop\n",
494 channel->queue_index);
499 struct xlgmac_channel *channel;
503 /* Enable each Tx DMA channel */
504 channel = pdata->channel_head;
505 for (i = 0; i < pdata->channel_count; i++, channel++) {
506 if (!channel->tx_ring)
509 regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_TCR));
512 writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_TCR));
533 struct xlgmac_channel *channel;
537 /* Prepare for Tx DMA channel stop */
538 channel = pdata->channel_head;
539 for (i = 0; i < pdata->channel_count; i++, channel++) {
540 if (!channel->tx_ring)
543 xlgmac_prepare_tx_stop(pdata, channel);
560 /* Disable each Tx DMA channel */
561 channel = pdata->channel_head;
562 for (i = 0; i < pdata->channel_count; i++, channel++) {
563 if (!channel->tx_ring)
566 regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_TCR));
569 writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_TCR));
604 struct xlgmac_channel *channel;
607 /* Enable each Rx DMA channel */
608 channel = pdata->channel_head;
609 for (i = 0; i < pdata->channel_count; i++, channel++) {
610 if (!channel->rx_ring)
613 regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_RCR));
616 writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_RCR));
640 struct xlgmac_channel *channel;
656 /* Prepare for Rx DMA channel stop */
663 /* Disable each Rx DMA channel */
664 channel = pdata->channel_head;
665 for (i = 0; i < pdata->channel_count; i++, channel++) {
666 if (!channel->rx_ring)
669 regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_RCR));
672 writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_RCR));
676 static void xlgmac_tx_start_xmit(struct xlgmac_channel *channel,
679 struct xlgmac_pdata *pdata = channel->pdata;
690 XLGMAC_DMA_REG(channel, DMA_CH_TDTR_LO));
693 if (pdata->tx_usecs && !channel->tx_timer_active) {
694 channel->tx_timer_active = 1;
695 mod_timer(&channel->tx_timer,
702 static void xlgmac_dev_xmit(struct xlgmac_channel *channel)
704 struct xlgmac_pdata *pdata = channel->pdata;
705 struct xlgmac_ring *ring = channel->tx_ring;
1000 channel->queue_index)))
1001 xlgmac_tx_start_xmit(channel, ring);
1006 channel->name, start_index & (ring->dma_desc_count - 1),
1056 static void xlgmac_tx_desc_init(struct xlgmac_channel *channel)
1058 struct xlgmac_ring *ring = channel->tx_ring;
1072 writel(ring->dma_desc_count - 1, XLGMAC_DMA_REG(channel, DMA_CH_TDRLR));
1077 XLGMAC_DMA_REG(channel, DMA_CH_TDLR_HI));
1079 XLGMAC_DMA_REG(channel, DMA_CH_TDLR_LO));
1139 static void xlgmac_rx_desc_init(struct xlgmac_channel *channel)
1141 struct xlgmac_pdata *pdata = channel->pdata;
1142 struct xlgmac_ring *ring = channel->rx_ring;
1156 writel(ring->dma_desc_count - 1, XLGMAC_DMA_REG(channel, DMA_CH_RDRLR));
1161 XLGMAC_DMA_REG(channel, DMA_CH_RDLR_HI));
1163 XLGMAC_DMA_REG(channel, DMA_CH_RDLR_LO));
1169 XLGMAC_DMA_REG(channel, DMA_CH_RDTR_LO));
1302 struct xlgmac_channel *channel;
1306 channel = pdata->channel_head;
1307 for (i = 0; i < pdata->channel_count; i++, channel++) {
1308 if (!channel->rx_ring)
1311 regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_RIWT));
1315 writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_RIWT));
1360 struct xlgmac_channel *channel;
1364 channel = pdata->channel_head;
1365 for (i = 0; i < pdata->channel_count; i++, channel++) {
1366 if (!channel->rx_ring)
1369 regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_RCR));
1373 writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_RCR));
1379 struct xlgmac_channel *channel;
1383 channel = pdata->channel_head;
1384 for (i = 0; i < pdata->channel_count; i++, channel++) {
1385 if (!channel->tx_ring)
1389 regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_TCR));
1392 writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_TCR));
1399 struct xlgmac_channel *channel;
1403 channel = pdata->channel_head;
1404 for (i = 0; i < pdata->channel_count; i++, channel++) {
1405 if (!channel->rx_ring)
1408 regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_CR));
1411 writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_CR));
1582 /* Configure one to one, MTL Rx queue to DMA Rx channel mapping
1741 struct xlgmac_channel *channel;
1745 channel = pdata->channel_head;
1746 for (i = 0; i < pdata->channel_count; i++, channel++) {
1747 if (!channel->tx_ring)
1750 regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_TCR));
1754 writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_TCR));
1762 struct xlgmac_channel *channel;
1766 channel = pdata->channel_head;
1767 for (i = 0; i < pdata->channel_count; i++, channel++) {
1768 regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_CR));
1772 writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_CR));
1790 struct xlgmac_channel *channel;
1794 channel = pdata->channel_head;
1795 for (i = 0; i < pdata->channel_count; i++, channel++) {
1796 if (!channel->tx_ring)
1799 regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_TCR));
1803 writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_TCR));
1821 struct xlgmac_channel *channel;
1825 channel = pdata->channel_head;
1826 for (i = 0; i < pdata->channel_count; i++, channel++) {
1827 if (!channel->rx_ring)
1830 regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_RCR));
1834 writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_RCR));
2449 struct xlgmac_channel *channel;
2452 channel = pdata->channel_head;
2453 for (i = 0; i < pdata->channel_count; i++, channel++) {
2455 dma_ch_isr = readl(XLGMAC_DMA_REG(channel, DMA_CH_SR));
2456 writel(dma_ch_isr, XLGMAC_DMA_REG(channel, DMA_CH_SR));
2476 if (channel->tx_ring) {
2479 * per channel interrupts)
2488 if (channel->rx_ring) {
2492 * per channel interrupts)
2507 writel(dma_ch_isr, XLGMAC_DMA_REG(channel, DMA_CH_IER));
2638 static int xlgmac_dev_read(struct xlgmac_channel *channel)
2640 struct xlgmac_pdata *pdata = channel->pdata;
2641 struct xlgmac_ring *ring = channel->rx_ring;
2810 XLGMAC_PR("%s - descriptor=%u (cur=%d)\n", channel->name,
2816 static int xlgmac_enable_int(struct xlgmac_channel *channel,
2821 dma_ch_ier = readl(XLGMAC_DMA_REG(channel, DMA_CH_IER));
2868 dma_ch_ier |= channel->saved_ier;
2874 writel(dma_ch_ier, XLGMAC_DMA_REG(channel, DMA_CH_IER));
2879 static int xlgmac_disable_int(struct xlgmac_channel *channel,
2884 dma_ch_ier = readl(XLGMAC_DMA_REG(channel, DMA_CH_IER));
2931 channel->saved_ier = dma_ch_ier & XLGMAC_DMA_INTERRUPT_MASK;
2938 writel(dma_ch_ier, XLGMAC_DMA_REG(channel, DMA_CH_IER));