Lines Matching defs:comm
16 void spl2sw_mac_hw_stop(struct spl2sw_common *comm)
20 if (comm->enable == 0) {
22 writel(0xffffffff, comm->l2sw_reg_base + L2SW_SW_INT_MASK_0);
23 writel(0xffffffff, comm->l2sw_reg_base + L2SW_SW_INT_STATUS_0);
26 reg = readl(comm->l2sw_reg_base + L2SW_CPU_CNTL);
28 writel(reg, comm->l2sw_reg_base + L2SW_CPU_CNTL);
32 reg = readl(comm->l2sw_reg_base + L2SW_PORT_CNTL0);
33 reg |= FIELD_PREP(MAC_DIS_PORT, ~comm->enable);
34 writel(reg, comm->l2sw_reg_base + L2SW_PORT_CNTL0);
37 void spl2sw_mac_hw_start(struct spl2sw_common *comm)
42 reg = readl(comm->l2sw_reg_base + L2SW_CPU_CNTL);
45 writel(reg, comm->l2sw_reg_base + L2SW_CPU_CNTL);
48 reg = readl(comm->l2sw_reg_base + L2SW_PORT_CNTL0);
49 reg &= FIELD_PREP(MAC_DIS_PORT, ~comm->enable) | ~MAC_DIS_PORT;
50 writel(reg, comm->l2sw_reg_base + L2SW_PORT_CNTL0);
55 struct spl2sw_common *comm = mac->comm;
61 comm->l2sw_reg_base + L2SW_W_MAC_15_0);
64 comm->l2sw_reg_base + L2SW_W_MAC_47_16);
69 writel(reg, comm->l2sw_reg_base + L2SW_WT_MAC_AD0);
73 comm->l2sw_reg_base + L2SW_WT_MAC_AD0);
80 readl(comm->l2sw_reg_base + L2SW_WT_MAC_AD0),
82 readl(comm->l2sw_reg_base + L2SW_W_MAC_47_16)),
84 readl(comm->l2sw_reg_base + L2SW_W_MAC_15_0)));
90 struct spl2sw_common *comm = mac->comm;
96 comm->l2sw_reg_base + L2SW_W_MAC_15_0);
99 comm->l2sw_reg_base + L2SW_W_MAC_47_16);
105 writel(reg, comm->l2sw_reg_base + L2SW_WT_MAC_AD0);
109 comm->l2sw_reg_base + L2SW_WT_MAC_AD0);
116 readl(comm->l2sw_reg_base + L2SW_WT_MAC_AD0),
118 readl(comm->l2sw_reg_base + L2SW_W_MAC_47_16)),
120 readl(comm->l2sw_reg_base + L2SW_W_MAC_15_0)));
124 void spl2sw_mac_hw_init(struct spl2sw_common *comm)
129 reg = readl(comm->l2sw_reg_base + L2SW_CPU_CNTL);
131 writel(reg, comm->l2sw_reg_base + L2SW_CPU_CNTL);
134 writel(comm->desc_dma, comm->l2sw_reg_base + L2SW_TX_LBASE_ADDR_0);
135 writel(comm->desc_dma + sizeof(struct spl2sw_mac_desc) * TX_DESC_NUM,
136 comm->l2sw_reg_base + L2SW_TX_HBASE_ADDR_0);
137 writel(comm->desc_dma + sizeof(struct spl2sw_mac_desc) * (TX_DESC_NUM +
138 MAC_GUARD_DESC_NUM), comm->l2sw_reg_base + L2SW_RX_HBASE_ADDR_0);
139 writel(comm->desc_dma + sizeof(struct spl2sw_mac_desc) * (TX_DESC_NUM +
141 comm->l2sw_reg_base + L2SW_RX_LBASE_ADDR_0);
144 writel(0x4a3a2d1d, comm->l2sw_reg_base + L2SW_FL_CNTL_TH);
147 writel(0x4a3a1212, comm->l2sw_reg_base + L2SW_CPU_FL_CNTL_TH);
150 writel(0xf6680000, comm->l2sw_reg_base + L2SW_PRI_FL_CNTL);
153 reg = readl(comm->l2sw_reg_base + L2SW_LED_PORT0);
155 writel(reg, comm->l2sw_reg_base + L2SW_LED_PORT0);
161 reg = readl(comm->l2sw_reg_base + L2SW_CPU_CNTL);
166 writel(reg, comm->l2sw_reg_base + L2SW_CPU_CNTL);
172 reg = readl(comm->l2sw_reg_base + L2SW_PORT_CNTL0);
176 writel(reg, comm->l2sw_reg_base + L2SW_PORT_CNTL0);
179 reg = readl(comm->l2sw_reg_base + L2SW_PORT_CNTL1);
181 writel(reg, comm->l2sw_reg_base + L2SW_PORT_CNTL1);
186 reg = readl(comm->l2sw_reg_base + L2SW_MAC_FORCE_MODE);
190 writel(reg, comm->l2sw_reg_base + L2SW_MAC_FORCE_MODE);
196 writel(reg, comm->l2sw_reg_base + L2SW_PVID_CONFIG0);
202 writel(reg, comm->l2sw_reg_base + L2SW_VLAN_MEMSET_CONFIG0);
208 reg = readl(comm->l2sw_reg_base + L2SW_SW_GLB_CNTL);
213 writel(reg, comm->l2sw_reg_base + L2SW_SW_GLB_CNTL);
215 writel(MAC_INT_MASK_DEF, comm->l2sw_reg_base + L2SW_SW_INT_MASK_0);
220 struct spl2sw_common *comm = mac->comm;
227 reg = readl(comm->l2sw_reg_base + L2SW_CPU_CNTL);
242 writel((reg & (~mask)) | ((~rx_mode) & mask), comm->l2sw_reg_base + L2SW_CPU_CNTL);
243 netdev_dbg(ndev, "cpu_cntl = %08x\n", readl(comm->l2sw_reg_base + L2SW_CPU_CNTL));
246 void spl2sw_mac_init(struct spl2sw_common *comm)
251 comm->rx_pos[i] = 0;
254 spl2sw_mac_hw_init(comm);
257 void spl2sw_mac_soft_reset(struct spl2sw_common *comm)
261 spl2sw_mac_hw_stop(comm);
263 spl2sw_rx_descs_flush(comm);
264 comm->tx_pos = 0;
265 comm->tx_done_pos = 0;
266 comm->tx_desc_full = 0;
269 comm->rx_pos[i] = 0;
272 spl2sw_mac_hw_init(comm);
273 spl2sw_mac_hw_start(comm);