Lines Matching refs:regs
127 writel(cmd, gp->regs + MIF_FRAME);
130 cmd = readl(gp->regs + MIF_FRAME);
165 writel(cmd, gp->regs + MIF_FRAME);
168 cmd = readl(gp->regs + MIF_FRAME);
190 writel(GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
196 writel(GREG_STAT_NAPI | GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
197 (void)readl(gp->regs + GREG_IMASK); /* write posting */
258 u32 pcs_istat = readl(gp->regs + PCS_ISTAT);
274 pcs_miistat = readl(gp->regs + PCS_MIISTAT);
277 (readl(gp->regs + PCS_MIISTAT) &
308 u32 txmac_stat = readl(gp->regs + MAC_TXSTAT);
367 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
369 if (!(readl(gp->regs + MAC_RXRST) & MAC_RXRST_CMD))
379 gp->regs + MAC_RXCFG);
381 if (!(readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB))
391 writel(0, gp->regs + RXDMA_CFG);
393 if (!(readl(gp->regs + RXDMA_CFG) & RXDMA_CFG_ENABLE))
406 gp->regs + GREG_SWRST);
408 if (!(readl(gp->regs + GREG_SWRST) & GREG_SWRST_RXRST))
433 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
434 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
435 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
438 writel(val, gp->regs + RXDMA_CFG);
439 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
442 gp->regs + RXDMA_BLANK);
446 gp->regs + RXDMA_BLANK);
449 writel(val, gp->regs + RXDMA_PTHRESH);
450 val = readl(gp->regs + RXDMA_CFG);
451 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
452 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
453 val = readl(gp->regs + MAC_RXCFG);
454 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
461 u32 rxmac_stat = readl(gp->regs + MAC_RXSTAT);
469 u32 smac = readl(gp->regs + MAC_SMACHINE);
495 u32 mac_cstat = readl(gp->regs + MAC_CSTAT);
516 u32 mif_status = readl(gp->regs + MIF_STATUS);
529 u32 pci_estat = readl(gp->regs + GREG_PCIESTAT);
728 writel(kick, gp->regs + RXDMA_KICK);
754 gp->dev->name, readl(gp->regs + RXDMA_DONE), gp->rx_new);
758 done = readl(gp->regs + RXDMA_DONE);
780 done = readl(gp->regs + RXDMA_DONE);
915 gp->status = readl(gp->regs + GREG_STAT);
930 u32 gem_status = readl(gp->regs + GREG_STAT);
970 readl(gp->regs + TXDMA_CFG),
971 readl(gp->regs + MAC_TXSTAT),
972 readl(gp->regs + MAC_TXCFG));
974 readl(gp->regs + RXDMA_CFG),
975 readl(gp->regs + MAC_RXSTAT),
976 readl(gp->regs + MAC_RXCFG));
1104 writel(gp->tx_new, gp->regs + TXDMA_KICK);
1115 val = readl(gp->regs + PCS_MIICTRL);
1117 writel(val, gp->regs + PCS_MIICTRL);
1120 while (readl(gp->regs + PCS_MIICTRL) & PCS_MIICTRL_RST) {
1136 val = readl(gp->regs + PCS_CFG);
1138 writel(val, gp->regs + PCS_CFG);
1143 val = readl(gp->regs + PCS_MIIADV);
1146 writel(val, gp->regs + PCS_MIIADV);
1151 val = readl(gp->regs + PCS_MIICTRL);
1154 writel(val, gp->regs + PCS_MIICTRL);
1156 val = readl(gp->regs + PCS_CFG);
1158 writel(val, gp->regs + PCS_CFG);
1164 val = readl(gp->regs + PCS_SCTRL);
1169 writel(val, gp->regs + PCS_SCTRL);
1180 writel(0xffffffff, gp->regs + GREG_IMASK);
1184 gp->regs + GREG_SWRST);
1190 val = readl(gp->regs + GREG_SWRST);
1207 val = readl(gp->regs + TXDMA_CFG);
1208 writel(val | TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
1209 val = readl(gp->regs + RXDMA_CFG);
1210 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
1211 val = readl(gp->regs + MAC_TXCFG);
1212 writel(val | MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
1213 val = readl(gp->regs + MAC_RXCFG);
1214 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1216 (void) readl(gp->regs + MAC_RXCFG);
1221 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1231 val = readl(gp->regs + TXDMA_CFG);
1232 writel(val & ~TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
1233 val = readl(gp->regs + RXDMA_CFG);
1234 writel(val & ~RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
1235 val = readl(gp->regs + MAC_TXCFG);
1236 writel(val & ~MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
1237 val = readl(gp->regs + MAC_RXCFG);
1238 writel(val & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1240 (void) readl(gp->regs + MAC_RXCFG);
1356 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1378 writel(val, gp->regs + MAC_TXCFG);
1392 writel(val, gp->regs + MAC_XIFCFG);
1398 val = readl(gp->regs + MAC_TXCFG);
1399 writel(val | MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1401 val = readl(gp->regs + MAC_RXCFG);
1402 writel(val | MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1404 val = readl(gp->regs + MAC_TXCFG);
1405 writel(val & ~MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1407 val = readl(gp->regs + MAC_RXCFG);
1408 writel(val & ~MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1413 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1420 writel(512, gp->regs + MAC_STIME);
1422 writel(64, gp->regs + MAC_STIME);
1423 val = readl(gp->regs + MAC_MCCFG);
1428 writel(val, gp->regs + MAC_MCCFG);
1505 u32 val = readl(gp->regs + PCS_MIISTAT);
1508 val = readl(gp->regs + PCS_MIISTAT);
1670 mifcfg = readl(gp->regs + MIF_CFG);
1672 writel(mifcfg, gp->regs + MIF_CFG);
1712 writel(val, gp->regs + PCS_DMODE);
1748 writel(val, gp->regs + TXDMA_CFG);
1750 writel(desc_dma >> 32, gp->regs + TXDMA_DBHI);
1751 writel(desc_dma & 0xffffffff, gp->regs + TXDMA_DBLOW);
1754 writel(0, gp->regs + TXDMA_KICK);
1758 writel(val, gp->regs + RXDMA_CFG);
1760 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
1761 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
1763 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1767 writel(val, gp->regs + RXDMA_PTHRESH);
1769 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
1772 gp->regs + RXDMA_BLANK);
1776 gp->regs + RXDMA_BLANK);
1787 writel(0xffff, gp->regs + MAC_HASH0 + (i << 2));
1804 writel(hash_table[i], gp->regs + MAC_HASH0 + (i << 2));
1815 writel(0x1bf0, gp->regs + MAC_SNDPAUSE);
1817 writel(0x00, gp->regs + MAC_IPG0);
1818 writel(0x08, gp->regs + MAC_IPG1);
1819 writel(0x04, gp->regs + MAC_IPG2);
1820 writel(0x40, gp->regs + MAC_STIME);
1821 writel(0x40, gp->regs + MAC_MINFSZ);
1824 writel(0x20000000 | (gp->rx_buf_sz + 4), gp->regs + MAC_MAXFSZ);
1826 writel(0x07, gp->regs + MAC_PASIZE);
1827 writel(0x04, gp->regs + MAC_JAMSIZE);
1828 writel(0x10, gp->regs + MAC_ATTLIM);
1829 writel(0x8808, gp->regs + MAC_MCTYPE);
1831 writel((e[5] | (e[4] << 8)) & 0x3ff, gp->regs + MAC_RANDSEED);
1833 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
1834 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
1835 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
1837 writel(0, gp->regs + MAC_ADDR3);
1838 writel(0, gp->regs + MAC_ADDR4);
1839 writel(0, gp->regs + MAC_ADDR5);
1841 writel(0x0001, gp->regs + MAC_ADDR6);
1842 writel(0xc200, gp->regs + MAC_ADDR7);
1843 writel(0x0180, gp->regs + MAC_ADDR8);
1845 writel(0, gp->regs + MAC_AFILT0);
1846 writel(0, gp->regs + MAC_AFILT1);
1847 writel(0, gp->regs + MAC_AFILT2);
1848 writel(0, gp->regs + MAC_AF21MSK);
1849 writel(0, gp->regs + MAC_AF0MSK);
1855 writel(0, gp->regs + MAC_NCOLL);
1856 writel(0, gp->regs + MAC_FASUCC);
1857 writel(0, gp->regs + MAC_ECOLL);
1858 writel(0, gp->regs + MAC_LCOLL);
1859 writel(0, gp->regs + MAC_DTIMER);
1860 writel(0, gp->regs + MAC_PATMPS);
1861 writel(0, gp->regs + MAC_RFCTR);
1862 writel(0, gp->regs + MAC_LERR);
1863 writel(0, gp->regs + MAC_AERR);
1864 writel(0, gp->regs + MAC_FCSERR);
1865 writel(0, gp->regs + MAC_RXCVERR);
1870 writel(0, gp->regs + MAC_TXCFG);
1871 writel(gp->mac_rx_cfg, gp->regs + MAC_RXCFG);
1872 writel(0, gp->regs + MAC_MCCFG);
1873 writel(0, gp->regs + MAC_XIFCFG);
1879 writel(MAC_TXSTAT_XMIT, gp->regs + MAC_TXMASK);
1880 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
1885 writel(0xffffffff, gp->regs + MAC_MCMASK);
1890 writel(0, gp->regs + WOL_WAKECSR);
1925 writel(cfg, gp->regs + GREG_CFG);
1930 if (!(readl(gp->regs + GREG_CFG) & GREG_CFG_IBURST)) {
1933 writel(cfg, gp->regs + GREG_CFG);
1948 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
1949 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
1952 mif_cfg = readl(gp->regs + MIF_CFG);
1955 writel(mif_cfg, gp->regs + MIF_CFG);
1956 writel(PCS_DMODE_MGM, gp->regs + PCS_DMODE);
1957 writel(MAC_XIFCFG_OE, gp->regs + MAC_XIFCFG);
1971 mif_cfg = readl(gp->regs + MIF_CFG);
1992 writel(mif_cfg, gp->regs + MIF_CFG);
1996 writel(mif_cfg, gp->regs + MIF_CFG);
2027 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
2028 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
2085 mifcfg = readl(gp->regs + MIF_CFG);
2087 writel(mifcfg, gp->regs + MIF_CFG);
2095 gp->regs + MAC_RXCFG);
2096 writel((e[4] << 8) | e[5], gp->regs + WOL_MATCH0);
2097 writel((e[2] << 8) | e[3], gp->regs + WOL_MATCH1);
2098 writel((e[0] << 8) | e[1], gp->regs + WOL_MATCH2);
2100 writel(WOL_MCOUNT_N | WOL_MCOUNT_M, gp->regs + WOL_MCOUNT);
2102 if ((readl(gp->regs + MAC_XIFCFG) & MAC_XIFCFG_GMII) == 0)
2104 writel(csr, gp->regs + WOL_WAKECSR);
2106 writel(0, gp->regs + MAC_RXCFG);
2107 (void)readl(gp->regs + MAC_RXCFG);
2115 writel(0, gp->regs + MAC_TXCFG);
2116 writel(0, gp->regs + MAC_XIFCFG);
2117 writel(0, gp->regs + TXDMA_CFG);
2118 writel(0, gp->regs + RXDMA_CFG);
2122 writel(MAC_TXRST_CMD, gp->regs + MAC_TXRST);
2123 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
2131 writel(mifcfg | MIF_CFG_BBMODE, gp->regs + MIF_CFG);
2132 writel(0, gp->regs + MIF_BBCLK);
2133 writel(0, gp->regs + MIF_BBDATA);
2134 writel(0, gp->regs + MIF_BBOENAB);
2135 writel(MAC_XIFCFG_GMII | MAC_XIFCFG_LBCK, gp->regs + MAC_XIFCFG);
2136 (void) readl(gp->regs + MAC_XIFCFG);
2413 dev->stats.rx_crc_errors += readl(gp->regs + MAC_FCSERR);
2414 writel(0, gp->regs + MAC_FCSERR);
2416 dev->stats.rx_frame_errors += readl(gp->regs + MAC_AERR);
2417 writel(0, gp->regs + MAC_AERR);
2419 dev->stats.rx_length_errors += readl(gp->regs + MAC_LERR);
2420 writel(0, gp->regs + MAC_LERR);
2422 dev->stats.tx_aborted_errors += readl(gp->regs + MAC_ECOLL);
2424 (readl(gp->regs + MAC_ECOLL) + readl(gp->regs + MAC_LCOLL));
2425 writel(0, gp->regs + MAC_ECOLL);
2426 writel(0, gp->regs + MAC_LCOLL);
2450 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
2451 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
2452 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
2470 rxcfg = readl(gp->regs + MAC_RXCFG);
2477 writel(rxcfg & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
2478 while (readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB) {
2487 writel(rxcfg, gp->regs + MAC_RXCFG);
2825 iounmap(gp->regs);
2928 gp->regs = ioremap(gemreg_base, gemreg_len);
2929 if (!gp->regs) {
3024 iounmap(gp->regs);