Lines Matching refs:val
75 static void writeq(u64 val, void __iomem *reg)
77 writel(val & 0xffffffff, reg);
78 writel(val >> 32, reg + 0x4UL);
92 #define nw64(reg, val) writeq((val), np->regs + (reg))
95 #define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg))
98 #define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg))
101 #define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg))
104 #define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg))
124 u64 val = nr64_mac(reg);
126 if (!(val & bits))
144 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
159 u64 val = nr64_ipp(reg);
161 if (!(val & bits))
175 u64 val;
177 val = nr64_ipp(reg);
178 val |= bits;
179 nw64_ipp(reg, val);
183 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
198 u64 val = nr64(reg);
200 if (!(val & bits))
223 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
236 u64 val = (u64) lp->timer;
239 val |= LDG_IMGMT_ARM;
241 nw64(LDG_IMGMT(lp->ldg_num), val);
247 u64 val;
260 val = nr64(mask_reg);
262 val &= ~bits;
264 val |= bits;
265 nw64(mask_reg, val);
311 static u32 phy_decode(u32 val, int port)
313 return (val >> (port * 2)) & PORT_TYPE_MASK;
319 u64 val;
322 val = nr64(MIF_FRAME_OUTPUT);
323 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
324 return val & MIF_FRAME_OUTPUT_DATA;
380 static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
386 val & 0xffff);
390 val >> 16);
394 static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
400 val & 0xffff);
404 val >> 16);
451 u64 sig, mask, val;
513 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
514 mask = val;
518 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
519 mask = val;
528 if ((sig & mask) == val)
534 if ((sig & mask) != val) {
536 np->port, (int)(sig & mask), (int)val);
548 u64 sig, mask, val;
608 val = (ESR_INT_SRDY0_P0 |
619 val = (ESR_INT_SRDY0_P1 |
634 if ((sig & mask) == val)
640 if ((sig & mask) != val) {
642 np->port, (int)(sig & mask), (int)val);
658 static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
664 *val = (err & 0xffff);
668 *val |= ((err & 0xffff) << 16);
674 static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
681 *val = (err & 0xffff);
685 *val |= ((err & 0xffff) << 16);
692 static int esr_read_reset(struct niu *np, u32 *val)
699 *val = (err & 0xffff);
703 *val |= ((err & 0xffff) << 16);
710 static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
715 ESR_RXTX_CTRL_L(chan), val & 0xffff);
718 ESR_RXTX_CTRL_H(chan), (val >> 16));
722 static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
727 ESR_GLUE_CTRL0_L(chan), val & 0xffff);
730 ESR_GLUE_CTRL0_H(chan), (val >> 16));
777 u64 ctrl_val, test_cfg_val, sig, mask, val;
861 val = (ESR_INT_SRDY0_P0 |
872 val = (ESR_INT_SRDY0_P1 |
885 if ((sig & mask) != val) {
891 np->port, (int)(sig & mask), (int)val);
901 u64 val;
903 val = nr64(ENET_SERDES_1_PLL_CFG);
904 val &= ~ENET_SERDES_PLL_FBDIV2;
907 val |= ENET_SERDES_PLL_HRATE0;
910 val |= ENET_SERDES_PLL_HRATE1;
913 val |= ENET_SERDES_PLL_HRATE2;
916 val |= ENET_SERDES_PLL_HRATE3;
921 nw64(ENET_SERDES_1_PLL_CFG, val);
930 u64 ctrl_val, test_cfg_val, sig, mask, val;
934 val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 |
983 nw64(pll_cfg, val);
1025 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
1026 mask = val;
1030 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
1031 mask = val;
1038 if ((sig & mask) != val) {
1040 np->port, (int)(sig & mask), (int)val);
1051 u64 val;
1062 val = nr64_pcs(PCS_MII_STAT);
1064 if (val & PCS_MII_STAT_LINK_STATUS) {
1084 u64 val, val2;
1095 val = nr64_xpcs(XPCS_STATUS(0));
1100 if ((val & 0x1000ULL) && link_ok) {
1393 static int mrvl88x2011_act_led(struct niu *np, int val)
1403 err |= MRVL88X2011_LED(MRVL88X2011_LED_ACT,val);
1557 u64 val;
1563 val = nr64_mac(XMAC_CONFIG);
1564 val &= ~XMAC_CONFIG_LED_POLARITY;
1565 val |= XMAC_CONFIG_FORCE_LED_ON;
1566 nw64_mac(XMAC_CONFIG, val);
1568 val = nr64(MIF_CONFIG);
1569 val |= MIF_CONFIG_INDIRECT_MODE;
1570 nw64(MIF_CONFIG, val);
1617 u64 val;
1619 val = nr64_mac(XMAC_CONFIG);
1620 val &= ~XMAC_CONFIG_LED_POLARITY;
1621 val |= XMAC_CONFIG_FORCE_LED_ON;
1622 nw64_mac(XMAC_CONFIG, val);
1625 val = nr64(MIF_CONFIG);
1626 val |= MIF_CONFIG_INDIRECT_MODE;
1627 nw64(MIF_CONFIG, val);
1675 u64 val;
1678 val = nr64(MIF_CONFIG);
1679 val &= ~MIF_CONFIG_INDIRECT_MODE;
1680 nw64(MIF_CONFIG, val);
1869 u64 val;
1872 val = nr64(MIF_CONFIG);
1873 val &= ~MIF_CONFIG_INDIRECT_MODE;
1874 nw64(MIF_CONFIG, val);
2125 u64 sig, mask, val;
2131 val = (ESR_INT_SRDY0_P0 |
2142 val = (ESR_INT_SRDY0_P1 |
2155 if ((sig & mask) != val)
2373 u64 ctrl_val, test_cfg_val, sig, mask, val;
2458 val = (ESR_INT_SRDY0_P0 |
2469 val = (ESR_INT_SRDY0_P1 |
2482 if ((sig & mask) != val) {
2675 u64 val, mask;
2688 val = nr64_mac(reg);
2690 val |= mask;
2692 val &= ~mask;
2693 nw64_mac(reg, val);
2701 u64 val = nr64_mac(reg);
2702 val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
2703 val |= num;
2705 val |= HOST_INFO_MPR;
2706 nw64_mac(reg, val);
2878 u64 val = nr64(FFLP_CFG_1);
2881 val &= ~FFLP_CFG_1_TCAM_DIS;
2883 val |= FFLP_CFG_1_TCAM_DIS;
2884 nw64(FFLP_CFG_1, val);
2889 u64 val = nr64(FFLP_CFG_1);
2891 val &= ~(FFLP_CFG_1_FFLPINITDONE |
2894 val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
2895 val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
2896 nw64(FFLP_CFG_1, val);
2898 val = nr64(FFLP_CFG_1);
2899 val |= FFLP_CFG_1_FFLPINITDONE;
2900 nw64(FFLP_CFG_1, val);
2907 u64 val;
2914 val = nr64(reg);
2916 val |= L2_CLS_VLD;
2918 val &= ~L2_CLS_VLD;
2919 nw64(reg, val);
2929 u64 val;
2937 val = nr64(reg);
2938 val &= ~L2_CLS_ETYPE;
2939 val |= (ether_type << L2_CLS_ETYPE_SHIFT);
2940 nw64(reg, val);
2950 u64 val;
2957 val = nr64(reg);
2959 val |= L3_CLS_VALID;
2961 val &= ~L3_CLS_VALID;
2962 nw64(reg, val);
2972 u64 val;
2982 val = nr64(reg);
2983 val &= ~(L3_CLS_IPVER | L3_CLS_PID |
2986 val |= L3_CLS_IPVER;
2987 val |= (protocol_id << L3_CLS_PID_SHIFT);
2988 val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
2989 val |= (tos_val << L3_CLS_TOS_SHIFT);
2990 nw64(reg, val);
3040 u64 val = hash_addr_regval(index, num_entries);
3047 nw64(HASH_TBL_ADDR(partition), val);
3059 u64 val = hash_addr_regval(index, num_entries);
3066 nw64(HASH_TBL_ADDR(partition), val);
3075 u64 val;
3081 val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
3082 nw64(FFLP_CFG_1, val);
3087 u64 val = nr64(FFLP_CFG_1);
3089 val &= ~FFLP_CFG_1_FFLPINITDONE;
3090 val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
3091 nw64(FFLP_CFG_1, val);
3093 val = nr64(FFLP_CFG_1);
3094 val |= FFLP_CFG_1_FFLPINITDONE;
3095 nw64(FFLP_CFG_1, val);
3097 val = nr64(FCRAM_REF_TMR);
3098 val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
3099 val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
3100 val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
3101 nw64(FCRAM_REF_TMR, val);
3108 u64 val;
3117 val = nr64(reg);
3118 val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
3119 val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
3120 val |= (base << FLW_PRT_SEL_BASE_SHIFT);
3122 val |= FLW_PRT_SEL_EXT;
3123 nw64(reg, val);
3142 u64 val = nr64(FFLP_CFG_1);
3145 val |= FFLP_CFG_1_LLCSNAP;
3147 val &= ~FFLP_CFG_1_LLCSNAP;
3148 nw64(FFLP_CFG_1, val);
3153 u64 val = nr64(FFLP_CFG_1);
3156 val &= ~FFLP_CFG_1_ERRORDIS;
3158 val |= FFLP_CFG_1_ERRORDIS;
3159 nw64(FFLP_CFG_1, val);
3391 u64 addr, val;
3396 val = le64_to_cpup(&rp->rcr[index]);
3397 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3401 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3414 if (!(val & RCR_ENTRY_MULTI))
3439 u64 addr, val, off;
3443 val = le64_to_cpup(&rp->rcr[index]);
3445 len = (val & RCR_ENTRY_L2_LEN) >>
3449 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3453 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3460 ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
3463 !(val & (RCR_ENTRY_NOPORT |
3468 } else if (!(val & RCR_ENTRY_MULTI))
3483 if (!(val & RCR_ENTRY_MULTI))
3922 u64 val;
3924 val = nr64_mac(XTXMAC_STATUS);
3925 if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
3927 if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
3929 if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
3931 if (val & XTXMAC_STATUS_TXMAC_OFLOW)
3933 if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
3935 if (val & XTXMAC_STATUS_TXMAC_UFLOW)
3938 val = nr64_mac(XRXMAC_STATUS);
3939 if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
3941 if (val & XRXMAC_STATUS_RFLT_DET)
3943 if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
3945 if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
3947 if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
3949 if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
3951 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3953 if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
3955 if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
3957 if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
3959 if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
3961 if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
3963 if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
3965 if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
3967 if (val & XRXMAC_STATUS_RXOCTET_CNT_EXP)
3969 if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
3971 if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
3973 if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
3975 if (val & XRXMAC_STATUS_RXUFLOW)
3977 if (val & XRXMAC_STATUS_RXOFLOW)
3980 val = nr64_mac(XMAC_FC_STAT);
3981 if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
3983 if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
3985 if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
3992 u64 val;
3994 val = nr64_mac(BTXMAC_STATUS);
3995 if (val & BTXMAC_STATUS_UNDERRUN)
3997 if (val & BTXMAC_STATUS_MAX_PKT_ERR)
3999 if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
4001 if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
4004 val = nr64_mac(BRXMAC_STATUS);
4005 if (val & BRXMAC_STATUS_OVERFLOW)
4007 if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
4009 if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
4011 if (val & BRXMAC_STATUS_CRC_ERR_EXP)
4013 if (val & BRXMAC_STATUS_LEN_ERR_EXP)
4016 val = nr64_mac(BMAC_CTRL_STATUS);
4017 if (val & BMAC_CTRL_STATUS_NOPAUSE)
4019 if (val & BMAC_CTRL_STATUS_PAUSE)
4021 if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
4563 u64 val = nr64(TX_CS(channel));
4564 if (val & TX_CS_SNG_STATE)
4572 u64 val = nr64(TX_CS(channel));
4574 val |= TX_CS_STOP_N_GO;
4575 nw64(TX_CS(channel), val);
4585 u64 val = nr64(TX_CS(channel));
4586 if (!(val & TX_CS_RST))
4594 u64 val = nr64(TX_CS(channel));
4597 val |= TX_CS_RST;
4598 nw64(TX_CS(channel), val);
4609 u64 val;
4619 val = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
4620 val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
4621 nw64(TX_LOG_PAGE_VLD(channel), val);
4631 u64 val, mask;
4634 val = nr64(TXC_CONTROL);
4637 val |= TXC_CONTROL_ENABLE | mask;
4639 val &= ~mask;
4640 if ((val & ~TXC_CONTROL_ENABLE) == 0)
4641 val &= ~TXC_CONTROL_ENABLE;
4643 nw64(TXC_CONTROL, val);
4650 u64 val;
4653 val = nr64(TXC_INT_MASK);
4654 val &= ~TXC_INT_MASK_VAL(np->port);
4655 val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
4661 u64 val = 0;
4667 val |= (1 << np->tx_rings[i].tx_channel);
4669 nw64(TXC_PORT_DMA(np->port), val);
4675 u64 val, ring_len;
4706 val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
4708 nw64(TX_RNG_CFIG(channel), val);
4747 u64 val;
4751 val = PT_DRR_WEIGHT_DEFAULT_10G;
4756 val = PT_DRR_WEIGHT_DEFAULT_1G;
4759 nw64(PT_DRR_WT(np->port), val);
4795 u64 val;
4805 val = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
4806 val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
4807 nw64(RX_LOG_PAGE_VLD(channel), val);
4814 u64 val;
4816 val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
4820 nw64(RDC_RED_PARA(rp->rx_channel), val);
4825 u64 val = 0;
4830 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
4833 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
4836 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
4839 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
4844 val |= RBR_CFIG_B_VLD2;
4847 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
4850 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
4853 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
4856 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
4862 val |= RBR_CFIG_B_VLD1;
4865 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
4868 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
4871 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
4874 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
4880 val |= RBR_CFIG_B_VLD0;
4883 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
4886 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
4889 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
4892 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
4899 *ret = val;
4905 u64 val = nr64(RXDMA_CFIG1(channel));
4909 val |= RXDMA_CFIG1_EN;
4911 val &= ~RXDMA_CFIG1_EN;
4912 nw64(RXDMA_CFIG1(channel), val);
4928 u64 val;
4953 err = niu_compute_rbr_cfig_b(rp, &val);
4956 nw64(RBR_CFIG_B(channel), val);
4971 val = nr64(RX_DMA_CTL_STAT(channel));
4972 val |= RX_DMA_CTL_STAT_RBR_EMPTY;
4973 nw64(RX_DMA_CTL_STAT(channel), val);
5141 u64 val = nr64(RESET_CFIFO);
5143 val |= RESET_CFIFO_RST(np->port);
5144 nw64(RESET_CFIFO, val);
5147 val &= ~RESET_CFIFO_RST(np->port);
5148 nw64(RESET_CFIFO, val);
5190 u64 val = nr64_ipp(IPP_CFIG);
5192 nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
5199 nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
5220 u64 data[5], rbuf[5], val;
5257 val = nr64_ipp(IPP_CFIG);
5258 val &= ~IPP_CFIG_IP_MAX_PKT;
5259 val |= (IPP_CFIG_IPP_ENABLE |
5264 nw64_ipp(IPP_CFIG, val);
5271 u64 val;
5272 val = nr64_mac(XMAC_CONFIG);
5277 val |= XMAC_CONFIG_LED_POLARITY;
5278 val &= ~XMAC_CONFIG_FORCE_LED_ON;
5280 val |= XMAC_CONFIG_FORCE_LED_ON;
5281 val &= ~XMAC_CONFIG_LED_POLARITY;
5285 nw64_mac(XMAC_CONFIG, val);
5291 u64 val;
5294 val = nr64(MIF_CONFIG);
5295 val |= MIF_CONFIG_ATCA_GE;
5296 nw64(MIF_CONFIG, val);
5299 val = nr64_mac(XMAC_CONFIG);
5300 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5302 val |= XMAC_CONFIG_TX_OUTPUT_EN;
5305 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5306 val |= XMAC_CONFIG_LOOPBACK;
5308 val &= ~XMAC_CONFIG_LOOPBACK;
5312 val &= ~XMAC_CONFIG_LFS_DISABLE;
5314 val |= XMAC_CONFIG_LFS_DISABLE;
5317 val |= XMAC_CONFIG_1G_PCS_BYPASS;
5319 val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
5322 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5325 val |= XMAC_CONFIG_SEL_CLK_25MHZ;
5327 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
5329 nw64_mac(XMAC_CONFIG, val);
5331 val = nr64_mac(XMAC_CONFIG);
5332 val &= ~XMAC_CONFIG_MODE_MASK;
5334 val |= XMAC_CONFIG_MODE_XGMII;
5337 val |= XMAC_CONFIG_MODE_GMII;
5339 val |= XMAC_CONFIG_MODE_MII;
5342 nw64_mac(XMAC_CONFIG, val);
5348 u64 val;
5350 val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
5353 val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
5355 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
5358 val |= BMAC_XIF_CONFIG_GMII_MODE;
5360 val &= ~BMAC_XIF_CONFIG_GMII_MODE;
5362 val &= ~(BMAC_XIF_CONFIG_LINK_LED |
5368 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
5370 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
5372 nw64_mac(BMAC_XIF_CONFIG, val);
5386 u64 val = nr64_pcs(PCS_MII_CTL);
5387 val |= PCS_MII_CTL_RST;
5388 nw64_pcs(PCS_MII_CTL, val);
5389 while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) {
5391 val = nr64_pcs(PCS_MII_CTL);
5398 u64 val = nr64_xpcs(XPCS_CONTROL1);
5399 val |= XPCS_CONTROL1_RESET;
5400 nw64_xpcs(XPCS_CONTROL1, val);
5401 while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) {
5403 val = nr64_xpcs(XPCS_CONTROL1);
5410 u64 val;
5430 val = nr64_mac(XMAC_CONFIG);
5431 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5432 nw64_mac(XMAC_CONFIG, val);
5436 val = nr64_xpcs(XPCS_CONTROL1);
5438 val |= XPCS_CONTROL1_LOOPBACK;
5440 val &= ~XPCS_CONTROL1_LOOPBACK;
5441 nw64_xpcs(XPCS_CONTROL1, val);
5510 u64 val;
5512 val = nr64_mac(XMAC_MIN);
5513 val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
5515 val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
5516 val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
5517 nw64_mac(XMAC_MIN, val);
5523 val = nr64_mac(XMAC_IPG);
5525 val &= ~XMAC_IPG_IPG_XGMII;
5526 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
5528 val &= ~XMAC_IPG_IPG_MII_GMII;
5529 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
5531 nw64_mac(XMAC_IPG, val);
5533 val = nr64_mac(XMAC_CONFIG);
5534 val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
5538 nw64_mac(XMAC_CONFIG, val);
5546 u64 val;
5555 val = nr64_mac(BTXMAC_CONFIG);
5556 val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
5558 nw64_mac(BTXMAC_CONFIG, val);
5640 u64 val;
5653 val = nr64_mac(XMAC_CONFIG);
5654 val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
5666 val |= (XMAC_CONFIG_HASH_FILTER_EN);
5667 nw64_mac(XMAC_CONFIG, val);
5692 u64 val;
5705 val = nr64_mac(BRXMAC_CONFIG);
5706 val &= ~(BRXMAC_CONFIG_ENABLE |
5713 val |= (BRXMAC_CONFIG_HASH_FILT_EN);
5714 nw64_mac(BRXMAC_CONFIG, val);
5716 val = nr64_mac(BMAC_ADDR_CMPEN);
5717 val |= BMAC_ADDR_CMPEN_EN0;
5718 nw64_mac(BMAC_ADDR_CMPEN, val);
5733 u64 val = nr64_mac(XMAC_CONFIG);
5736 val |= XMAC_CONFIG_TX_ENABLE;
5738 val &= ~XMAC_CONFIG_TX_ENABLE;
5739 nw64_mac(XMAC_CONFIG, val);
5744 u64 val = nr64_mac(BTXMAC_CONFIG);
5747 val |= BTXMAC_CONFIG_ENABLE;
5749 val &= ~BTXMAC_CONFIG_ENABLE;
5750 nw64_mac(BTXMAC_CONFIG, val);
5763 u64 val = nr64_mac(XMAC_CONFIG);
5765 val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
5769 val |= XMAC_CONFIG_HASH_FILTER_EN;
5771 val |= XMAC_CONFIG_PROMISCUOUS;
5774 val |= XMAC_CONFIG_RX_MAC_ENABLE;
5776 val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
5777 nw64_mac(XMAC_CONFIG, val);
5782 u64 val = nr64_mac(BRXMAC_CONFIG);
5784 val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
5788 val |= BRXMAC_CONFIG_HASH_FILT_EN;
5790 val |= BRXMAC_CONFIG_PROMISC;
5793 val |= BRXMAC_CONFIG_ENABLE;
5795 val &= ~BRXMAC_CONFIG_ENABLE;
5796 nw64_mac(BRXMAC_CONFIG, val);
5909 u64 rd, wr, val;
5926 val = nr64_ipp(IPP_CFIG);
5927 val &= ~(IPP_CFIG_IPP_ENABLE |
5931 nw64_ipp(IPP_CFIG, val);
6570 __be16 val = vp->h_vlan_encapsulated_proto;
6572 eth_proto_inner = be16_to_cpu(val);
6879 u32 offset, len, val;
6899 val = nr64(ESPC_NCR((offset - b_offset) / 4));
6900 memcpy(data, ((char *)&val) + b_offset, b_count);
6906 val = nr64(ESPC_NCR(offset / 4));
6907 memcpy(data, &val, 4);
6913 val = nr64(ESPC_NCR(offset / 4));
6914 memcpy(data, &val, len);
7838 static void niu_led_state_restore(struct niu *np, u64 val)
7841 nw64_mac(XMAC_CONFIG, val);
7843 nw64_mac(BMAC_XIF_CONFIG, val);
7848 u64 val, reg, bit;
7858 val = nr64_mac(reg);
7860 val |= bit;
7862 val &= ~bit;
7863 nw64_mac(reg, val);
8010 u16 val;
8014 val = (err << 8);
8018 val |= (err & 0xff);
8020 return val;
8026 u16 val;
8031 val = (err & 0xff);
8036 val |= (err & 0xff) << 8;
8038 return val;
8381 u64 val, sum;
8384 val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);
8385 val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT;
8386 len = val / 4;
8391 "SPROM: Image size %llu\n", (unsigned long long)val);
8395 val = nr64(ESPC_NCR(i));
8396 sum += (val >> 0) & 0xff;
8397 sum += (val >> 8) & 0xff;
8398 sum += (val >> 16) & 0xff;
8399 sum += (val >> 24) & 0xff;
8408 val = nr64(ESPC_PHY_TYPE);
8411 val8 = (val & ESPC_PHY_TYPE_PORT0) >>
8415 val8 = (val & ESPC_PHY_TYPE_PORT1) >>
8419 val8 = (val & ESPC_PHY_TYPE_PORT2) >>
8423 val8 = (val & ESPC_PHY_TYPE_PORT3) >>
8468 val = nr64(ESPC_MAC_ADDR0);
8470 "SPROM: MAC_ADDR0[%08llx]\n", (unsigned long long)val);
8471 addr[0] = (val >> 0) & 0xff;
8472 addr[1] = (val >> 8) & 0xff;
8473 addr[2] = (val >> 16) & 0xff;
8474 addr[3] = (val >> 24) & 0xff;
8476 val = nr64(ESPC_MAC_ADDR1);
8478 "SPROM: MAC_ADDR1[%08llx]\n", (unsigned long long)val);
8479 addr[4] = (val >> 0) & 0xff;
8480 addr[5] = (val >> 8) & 0xff;
8495 val = nr64(ESPC_MOD_STR_LEN);
8497 "SPROM: MOD_STR_LEN[%llu]\n", (unsigned long long)val);
8498 if (val >= 8 * 4)
8501 for (i = 0; i < val; i += 4) {
8509 np->vpd.model[val] = '\0';
8511 val = nr64(ESPC_BD_MOD_STR_LEN);
8513 "SPROM: BD_MOD_STR_LEN[%llu]\n", (unsigned long long)val);
8514 if (val >= 4 * 4)
8517 for (i = 0; i < val; i += 4) {
8525 np->vpd.board_model[val] = '\0';
8818 u32 val;
8829 val = (phy_encode(PORT_TYPE_1G, 0) |
8837 val = (phy_encode(PORT_TYPE_10G, 0) |
8843 val = (phy_encode(PORT_TYPE_10G, 0) |
8846 val = (phy_encode(PORT_TYPE_1G, 0) |
8868 val = (phy_encode(PORT_TYPE_10G, 0) |
8875 val = (phy_encode(PORT_TYPE_10G, 0) |
8880 val = phy_encode(PORT_TYPE_10G, np->port);
8894 val = (phy_encode(PORT_TYPE_10G, 0) |
8899 val = (phy_encode(PORT_TYPE_1G, 0) |
8913 val = (phy_encode(PORT_TYPE_1G, 0) |
8926 parent->port_phy = val;