Lines Matching refs:port
306 static u32 phy_encode(u32 type, int port)
308 return type << (port * 2);
311 static u32 phy_decode(u32 val, int port)
313 return (val >> (port * 2)) & PORT_TYPE_MASK;
332 static int mdio_read(struct niu *np, int port, int dev, int reg)
336 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
341 nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
345 static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
349 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
354 nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
362 static int mii_read(struct niu *np, int port, int reg)
364 nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
368 static int mii_write(struct niu *np, int port, int reg, int data)
372 nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
384 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
388 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
398 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
402 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
423 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
462 if (np->port == 0)
468 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
478 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
482 np->port, __func__);
488 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
492 np->port, __func__);
511 switch (np->port) {
536 np->port, (int)(sig & mask), (int)val);
560 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
570 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
574 np->port, __func__);
580 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
584 np->port, __func__);
605 switch (np->port) {
642 np->port, (int)(sig & mask), (int)val);
651 np->port);
662 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
665 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
678 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
682 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
696 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
700 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
714 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
717 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
726 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
729 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
739 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
743 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
749 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
755 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
766 np->port, reset);
780 switch (np->port) {
858 switch (np->port) {
891 np->port, (int)(sig & mask), (int)val);
905 switch (np->port) {
937 switch (np->port) {
1023 switch (np->port) {
1040 np->port, (int)(sig & mask), (int)val);
1301 np->port, (err & 0xffff));
1483 pr_info("Port %u PMA_PMD(MII_STAT1000) [%04x]\n", np->port, err);
1488 pr_info("Port %u USER_DEV3(0x20) [%04x]\n", np->port, err);
1494 pr_info("Port %u PHYXS(MII_NWAYTEST) [%04x]\n", np->port, err);
1521 np->port);
1524 np->port);
1629 phy_id = phy_decode(np->parent->port_phy, np->port);
1630 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1665 np->port, err);
1861 np->port, bmcr, bmsr);
2103 phy_id = phy_decode(np->parent->port_phy, np->port);
2104 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
2128 switch (np->port) {
2375 switch (np->port) {
2455 switch (np->port) {
2490 np->port);
2523 if (np->port == 0)
2525 if (np->port == 1)
2529 phy_addr_off += np->port;
2546 phy_addr_off += (np->port ^ 0x3);
2565 phy_addr_off += np->port;
2568 if (np->port == 0)
2570 if (np->port == 1)
2578 switch(np->port) {
2590 phy_addr_off = niu_atca_port_num[np->port];
2767 int port, int vpr, int rdc_table)
2773 ENET_VLAN_TBL_SHIFT(port));
2776 ENET_VLAN_TBL_SHIFT(port));
2777 reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
4476 int i, port, err;
4478 port = np->port;
4480 for (i = 0; i < port; i++) {
4485 num_rx_rings = parent->rxchan_per_port[port];
4486 num_tx_rings = parent->txchan_per_port[port];
4619 val = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
4635 mask = (u64)1 << np->port;
4654 val &= ~TXC_INT_MASK_VAL(np->port);
4655 val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
4669 nw64(TXC_PORT_DMA(np->port), val);
4728 struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
4741 nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
4746 int type = phy_decode(np->parent->port_phy, np->port);
4759 nw64(PT_DRR_WT(np->port), val);
4765 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4805 val = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
5055 vlan_tbl_write(np, i, np->port,
5099 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5120 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5143 val |= RESET_CFIFO_RST(np->port);
5147 val &= ~RESET_CFIFO_RST(np->port);
5157 if (np->port == 0 || np->port == 1)
5180 nw64(CFIFO_ECC(np->port), 0);
5224 if (np->port == 0 || np->port == 1)
5492 np->port,
5597 np->port,
5618 np->port,
5637 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5689 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
6024 int port = np->port;
6029 if (port == 0) {
6827 cmd->base.port = (np->flags & NIU_FLAGS_FIBER) ? PORT_FIBRE : PORT_TP;
7433 struct niu_rdc_tables *rdc_table = &parent->rdc_group_cfg[np->port];
7931 np->port, ldn, ldg,
8349 if (np->port > 1) {
8369 addr[5] += np->port;
8409 switch (np->port) {
8427 dev_err(np->device, "Bogus port number %u\n",
8428 np->port);
8489 addr[5] += np->port;
8539 if (np->port <= 1)
8563 if (np->port >= parent->num_ports)
8606 static int port_has_10g(struct phy_probe_info *p, int port)
8611 if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port)
8615 if (p->phy_port[PHY_TYPE_PCS][i] == port)
8624 int port, cnt;
8628 for (port = 8; port < 32; port++) {
8629 if (port_has_10g(p, port)) {
8631 *lowest = port;
8709 pr_err("niu%d: Too many RX channels (%d), resetting to one per port\n",
8715 pr_err("niu%d: Too many TX channels (%d), resetting to one per port\n",
8775 int port, err;
8782 for (port = 8; port < 32; port++) {
8785 dev_id_1 = mdio_read(np, port,
8787 dev_id_2 = mdio_read(np, port,
8789 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8793 dev_id_1 = mdio_read(np, port,
8795 dev_id_2 = mdio_read(np, port,
8797 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8801 dev_id_1 = mii_read(np, port, MII_PHYSID1);
8802 dev_id_2 = mii_read(np, port, MII_PHYSID2);
8803 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8880 val = phy_encode(PORT_TYPE_10G, np->port);
8920 pr_err("Unsupported port config 10G[%d] 1G[%d]\n",
8967 cp->tcam_top = (u16) np->port;
9002 switch (np->port) {
9032 dev_err(np->device, "Port %u is invalid, cannot compute MAC block offset\n", np->port);
9047 first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port;
9051 num_irqs = (parent->rxchan_per_port[np->port] +
9052 parent->txchan_per_port[np->port] +
9053 (np->port == 0 ? 3 : 1));
9103 u8 port;
9114 port = np->port;
9129 err = niu_set_ldg_sid(np, lp->ldg_num, port, i);
9140 * MIF (if port zero)
9141 * SYSERR (if port zero)
9149 LDN_MAC(port));
9157 if (port == 0) {
9181 for (i = 0; i < port; i++)
9183 num_chan = parent->rxchan_per_port[port];
9197 for (i = 0; i < port; i++)
9199 num_chan = parent->txchan_per_port[port];
9535 int port = np->port;
9552 sprintf(port_name, "port%d", port);
9557 p->ports[port] = np;
9569 u8 port = np->port;
9572 BUG_ON(!p || p->ports[port] != np);
9575 "%s() port[%u]\n", __func__, port);
9577 sprintf(port_name, "port%d", port);
9583 p->ports[port] = NULL;
9659 const struct niu_ops *ops, u8 port)
9682 np->port = port;