Lines Matching refs:nw64
92 #define nw64(reg, val) writeq((val), np->regs + (reg))
220 nw64(reg, bits);
241 nw64(LDG_IMGMT(lp->ldg_num), val);
265 nw64(mask_reg, val);
336 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
341 nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
349 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
354 nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
364 nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
372 nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
818 nw64(ctrl_reg, ctrl_val);
819 nw64(test_cfg_reg, test_cfg_val);
921 nw64(ENET_SERDES_1_PLL_CFG, val);
979 nw64(ENET_SERDES_RESET, reset_val);
983 nw64(pll_cfg, val);
984 nw64(ctrl_reg, ctrl_val);
985 nw64(test_cfg_reg, test_cfg_val);
986 nw64(ENET_SERDES_RESET, val_rd);
1570 nw64(MIF_CONFIG, val);
1627 nw64(MIF_CONFIG, val);
1680 nw64(MIF_CONFIG, val);
1874 nw64(MIF_CONFIG, val);
2416 nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2);
2417 nw64(ctrl_reg, ctrl_val);
2418 nw64(test_cfg_reg, test_cfg_val);
2781 nw64(ENET_VLAN_TBL(index), reg_val);
2789 nw64(ENET_VLAN_TBL(i), 0);
2809 nw64(TCAM_KEY_0, 0x00);
2810 nw64(TCAM_KEY_MASK_0, 0xff);
2811 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2822 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
2841 nw64(TCAM_KEY_0, key[0]);
2842 nw64(TCAM_KEY_1, key[1]);
2843 nw64(TCAM_KEY_2, key[2]);
2844 nw64(TCAM_KEY_3, key[3]);
2845 nw64(TCAM_KEY_MASK_0, mask[0]);
2846 nw64(TCAM_KEY_MASK_1, mask[1]);
2847 nw64(TCAM_KEY_MASK_2, mask[2]);
2848 nw64(TCAM_KEY_MASK_3, mask[3]);
2849 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2859 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
2870 nw64(TCAM_KEY_1, assoc_data);
2871 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
2884 nw64(FFLP_CFG_1, val);
2896 nw64(FFLP_CFG_1, val);
2900 nw64(FFLP_CFG_1, val);
2919 nw64(reg, val);
2940 nw64(reg, val);
2962 nw64(reg, val);
2990 nw64(reg, val);
3047 nw64(HASH_TBL_ADDR(partition), val);
3066 nw64(HASH_TBL_ADDR(partition), val);
3068 nw64(HASH_TBL_DATA(partition), data[i]);
3077 nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
3079 nw64(FFLP_CFG_1, 0);
3082 nw64(FFLP_CFG_1, val);
3091 nw64(FFLP_CFG_1, val);
3095 nw64(FFLP_CFG_1, val);
3101 nw64(FCRAM_REF_TMR, val);
3123 nw64(reg, val);
3148 nw64(FFLP_CFG_1, val);
3159 nw64(FFLP_CFG_1, val);
3210 nw64(H1POLY, 0);
3211 nw64(H2POLY, 0);
3244 nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3254 nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3377 nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
3656 * reading nr64() and clearing the counter nw64(). For this
3657 * reason, the number of counter clearings nw64() is
3670 nw64(RXMISC(rx_channel), 0);
3685 nw64(RED_DIS_CNT(rx_channel), 0);
3737 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
3760 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
3775 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
3851 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
4099 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
4150 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
4181 nw64(LD_IM0(ldn), LD_IM0_MASK);
4193 nw64(LD_IM0(ldn), LD_IM0_MASK);
4575 nw64(TX_CS(channel), val);
4598 nw64(TX_CS(channel), val);
4602 nw64(TX_RING_KICK(channel), 0);
4611 nw64(TX_LOG_MASK1(channel), 0);
4612 nw64(TX_LOG_VAL1(channel), 0);
4613 nw64(TX_LOG_MASK2(channel), 0);
4614 nw64(TX_LOG_VAL2(channel), 0);
4615 nw64(TX_LOG_PAGE_RELO1(channel), 0);
4616 nw64(TX_LOG_PAGE_RELO2(channel), 0);
4617 nw64(TX_LOG_PAGE_HDL(channel), 0);
4621 nw64(TX_LOG_PAGE_VLD(channel), val);
4643 nw64(TXC_CONTROL, val);
4669 nw64(TXC_PORT_DMA(np->port), val);
4689 nw64(TXC_DMA_MAX(channel), rp->max_burst);
4690 nw64(TX_ENT_MSK(channel), 0);
4708 nw64(TX_RNG_CFIG(channel), val);
4716 nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
4717 nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
4719 nw64(TX_CS(channel), 0);
4737 nw64(RDC_TBL(this_table, slot),
4741 nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
4759 nw64(PT_DRR_WT(np->port), val);
4797 nw64(RX_LOG_MASK1(channel), 0);
4798 nw64(RX_LOG_VAL1(channel), 0);
4799 nw64(RX_LOG_MASK2(channel), 0);
4800 nw64(RX_LOG_VAL2(channel), 0);
4801 nw64(RX_LOG_PAGE_RELO1(channel), 0);
4802 nw64(RX_LOG_PAGE_RELO2(channel), 0);
4803 nw64(RX_LOG_PAGE_HDL(channel), 0);
4807 nw64(RX_LOG_PAGE_VLD(channel), val);
4820 nw64(RDC_RED_PARA(rp->rx_channel), val);
4912 nw64(RXDMA_CFIG1(channel), val);
4940 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
4941 nw64(RX_DMA_CTL_STAT(channel),
4946 nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
4947 nw64(RXDMA_CFIG2(channel),
4950 nw64(RBR_CFIG_A(channel),
4956 nw64(RBR_CFIG_B(channel), val);
4957 nw64(RCRCFIG_A(channel),
4960 nw64(RCRCFIG_B(channel),
4969 nw64(RBR_KICK(channel), rp->rbr_index);
4973 nw64(RX_DMA_CTL_STAT(channel), val);
4985 nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
4986 nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
5045 nw64(H1POLY, cp->h1_init);
5046 nw64(H2POLY, cp->h2_init);
5090 nw64(ZCP_RAM_DATA0, data[0]);
5091 nw64(ZCP_RAM_DATA1, data[1]);
5092 nw64(ZCP_RAM_DATA2, data[2]);
5093 nw64(ZCP_RAM_DATA3, data[3]);
5094 nw64(ZCP_RAM_DATA4, data[4]);
5095 nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
5096 nw64(ZCP_RAM_ACC,
5117 nw64(ZCP_RAM_ACC,
5144 nw64(RESET_CFIFO, val);
5148 nw64(RESET_CFIFO, val);
5180 nw64(CFIFO_ECC(np->port), 0);
5181 nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
5183 nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
5296 nw64(MIF_CONFIG, val);
5891 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
5892 nw64(RX_DMA_CTL_STAT(channel), 0);
6729 nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3));
7328 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7340 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1),
7352 nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7936 nw64(LDG_NUM(ldn), ldg);
7947 nw64(LDG_TIMER_RES, res);
7959 nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector);
7974 nw64(ESPC_PIO_STAT, frame);
7989 nw64(ESPC_PIO_STAT, frame);
9309 nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE);
9318 nw64(ESPC_PIO_EN, 0);