Lines Matching defs:nr64
91 #define nr64(reg) readq(np->regs + (reg))
198 u64 val = nr64(reg);
225 (unsigned long long)nr64(reg));
260 val = nr64(mask_reg);
322 val = nr64(MIF_FRAME_OUTPUT);
527 sig = nr64(ESR_INT_SIGNALS);
633 sig = nr64(ESR_INT_SIGNALS);
857 sig = nr64(ESR_INT_SIGNALS);
903 val = nr64(ENET_SERDES_1_PLL_CFG);
981 val_rd = nr64(ENET_SERDES_RESET);
1022 sig = nr64(ESR_INT_SIGNALS);
1568 val = nr64(MIF_CONFIG);
1625 val = nr64(MIF_CONFIG);
1678 val = nr64(MIF_CONFIG);
1872 val = nr64(MIF_CONFIG);
2127 sig = nr64(ESR_INT_SIGNALS);
2454 sig = nr64(ESR_INT_SIGNALS);
2769 u64 reg_val = nr64(ENET_VLAN_TBL(index));
2797 if (nr64(TCAM_CTL) & bit)
2825 key[0] = nr64(TCAM_KEY_0);
2826 key[1] = nr64(TCAM_KEY_1);
2827 key[2] = nr64(TCAM_KEY_2);
2828 key[3] = nr64(TCAM_KEY_3);
2829 mask[0] = nr64(TCAM_KEY_MASK_0);
2830 mask[1] = nr64(TCAM_KEY_MASK_1);
2831 mask[2] = nr64(TCAM_KEY_MASK_2);
2832 mask[3] = nr64(TCAM_KEY_MASK_3);
2862 *data = nr64(TCAM_KEY_1);
2878 u64 val = nr64(FFLP_CFG_1);
2889 u64 val = nr64(FFLP_CFG_1);
2898 val = nr64(FFLP_CFG_1);
2914 val = nr64(reg);
2937 val = nr64(reg);
2957 val = nr64(reg);
2982 val = nr64(reg);
3049 data[i] = nr64(HASH_TBL_DATA(partition));
3087 u64 val = nr64(FFLP_CFG_1);
3093 val = nr64(FFLP_CFG_1);
3097 val = nr64(FCRAM_REF_TMR);
3117 val = nr64(reg);
3142 u64 val = nr64(FFLP_CFG_1);
3153 u64 val = nr64(FFLP_CFG_1);
3656 * reading nr64() and clearing the counter nw64(). For this
3668 misc = nr64(RXMISC(rx_channel));
3683 wred = nr64(RED_DIS_CNT(rx_channel));
3705 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3706 qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
3835 u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3886 cs = nr64(TX_CS(rp->tx_channel));
3887 logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
3888 logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
3903 u64 mif_status = nr64(MIF_STATUS);
4067 u64 stat = nr64(SYS_ERR_STAT);
4159 rp->tx_cs = nr64(TX_CS(rp->tx_channel));
4225 v0 = nr64(LDSV0(ldg));
4226 v1 = nr64(LDSV1(ldg));
4227 v2 = nr64(LDSV2(ldg));
4563 u64 val = nr64(TX_CS(channel));
4572 u64 val = nr64(TX_CS(channel));
4585 u64 val = nr64(TX_CS(channel));
4594 u64 val = nr64(TX_CS(channel));
4634 val = nr64(TXC_CONTROL);
4653 val = nr64(TXC_INT_MASK);
4905 u64 val = nr64(RXDMA_CFIG1(channel));
4916 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
4971 val = nr64(RX_DMA_CTL_STAT(channel));
5113 (unsigned long long)nr64(ZCP_RAM_ACC));
5126 (unsigned long long)nr64(ZCP_RAM_ACC));
5130 data[0] = nr64(ZCP_RAM_DATA0);
5131 data[1] = nr64(ZCP_RAM_DATA1);
5132 data[2] = nr64(ZCP_RAM_DATA2);
5133 data[3] = nr64(ZCP_RAM_DATA3);
5134 data[4] = nr64(ZCP_RAM_DATA4);
5141 u64 val = nr64(RESET_CFIFO);
5182 (void) nr64(ZCP_INT_STAT);
5294 val = nr64(MIF_CONFIG);
6899 val = nr64(ESPC_NCR((offset - b_offset) / 4));
6906 val = nr64(ESPC_NCR(offset / 4));
6913 val = nr64(ESPC_NCR(offset / 4));
7929 if (nr64(LDG_NUM(ldn)) != ldg) {
7932 (unsigned long long) nr64(LDG_NUM(ldn)));
7978 frame = nr64(ESPC_PIO_STAT);
7993 frame = nr64(ESPC_PIO_STAT);
8003 frame = nr64(ESPC_PIO_STAT);
8384 val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);
8395 val = nr64(ESPC_NCR(i));
8408 val = nr64(ESPC_PHY_TYPE);
8468 val = nr64(ESPC_MAC_ADDR0);
8476 val = nr64(ESPC_MAC_ADDR1);
8495 val = nr64(ESPC_MOD_STR_LEN);
8502 u64 tmp = nr64(ESPC_NCR(5 + (i / 4)));
8511 val = nr64(ESPC_BD_MOD_STR_LEN);
8518 u64 tmp = nr64(ESPC_NCR(14 + (i / 4)));
8528 nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL;
8551 parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) &