Lines Matching defs:err
139 int err;
142 err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
143 if (err)
147 return err;
174 int err;
181 err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
182 if (err)
186 return err;
218 int err;
221 err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
222 if (err)
226 return err;
276 int err;
281 err = niu_ldn_irq_enable(np, i, on);
282 if (err)
283 return err;
294 int err;
296 err = niu_enable_ldn_in_ldg(np, lp, on);
297 if (err)
298 return err;
334 int err;
337 err = mdio_wait(np);
338 if (err < 0)
339 return err;
347 int err;
350 err = mdio_wait(np);
351 if (err < 0)
352 return err;
355 err = mdio_wait(np);
356 if (err < 0)
357 return err;
370 int err;
373 err = mdio_wait(np);
374 if (err < 0)
375 return err;
382 int err;
384 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
387 if (!err)
388 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
391 return err;
396 int err;
398 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
401 if (!err)
402 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
405 return err;
432 int err = esr2_set_tx_cfg(np, i, tx_cfg);
433 if (err)
434 return err;
438 int err = esr2_set_rx_cfg(np, i, rx_cfg);
439 if (err)
440 return err;
454 int err;
478 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
480 if (err) {
483 return err;
488 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
490 if (err) {
493 return err;
500 err = esr2_set_tx_cfg(np, i, tx_cfg);
501 if (err)
502 return err;
506 err = esr2_set_rx_cfg(np, i, rx_cfg);
507 if (err)
508 return err;
550 int err;
570 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
572 if (err) {
575 return err;
580 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
582 if (err) {
585 return err;
592 err = esr2_set_tx_cfg(np, i, tx_cfg);
593 if (err)
594 return err;
598 err = esr2_set_rx_cfg(np, i, rx_cfg);
599 if (err)
600 return err;
645 err = serdes_init_niu_1g_serdes(np);
646 if (!err) {
660 int err;
662 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
663 if (err >= 0) {
664 *val = (err & 0xffff);
665 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
667 if (err >= 0)
668 *val |= ((err & 0xffff) << 16);
669 err = 0;
671 return err;
676 int err;
678 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
680 if (err >= 0) {
681 *val = (err & 0xffff);
682 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
684 if (err >= 0) {
685 *val |= ((err & 0xffff) << 16);
686 err = 0;
689 return err;
694 int err;
696 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
698 if (err >= 0) {
699 *val = (err & 0xffff);
700 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
702 if (err >= 0) {
703 *val |= ((err & 0xffff) << 16);
704 err = 0;
707 return err;
712 int err;
714 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
716 if (!err)
717 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
719 return err;
724 int err;
726 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
728 if (!err)
729 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
731 return err;
737 int err;
739 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
741 if (err)
742 return err;
743 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
745 if (err)
746 return err;
749 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
751 if (err)
752 return err;
755 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
757 if (err)
758 return err;
761 err = esr_read_reset(np, &reset);
762 if (err)
763 return err;
778 int err;
825 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
826 if (err)
827 return err;
828 err = esr_read_glue0(np, i, &glue0);
829 if (err)
830 return err;
845 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
846 if (err)
847 return err;
848 err = esr_write_glue0(np, i, glue0);
849 if (err)
850 return err;
853 err = esr_reset(np);
854 if (err)
855 return err;
931 int err;
993 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
994 if (err)
995 return err;
996 err = esr_read_glue0(np, i, &glue0);
997 if (err)
998 return err;
1013 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
1014 if (err)
1015 return err;
1016 err = esr_write_glue0(np, i, glue0);
1017 if (err)
1018 return err;
1115 int err;
1119 err = mii_read(np, np->phy_addr, MII_BMCR);
1120 if (unlikely(err < 0))
1121 return err;
1122 bmcr = err;
1124 err = mii_read(np, np->phy_addr, MII_BMSR);
1125 if (unlikely(err < 0))
1126 return err;
1127 bmsr = err;
1129 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1130 if (unlikely(err < 0))
1131 return err;
1132 advert = err;
1134 err = mii_read(np, np->phy_addr, MII_LPA);
1135 if (unlikely(err < 0))
1136 return err;
1137 lpa = err;
1140 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1141 if (unlikely(err < 0))
1142 return err;
1143 estatus = err;
1145 err = mii_read(np, np->phy_addr, MII_CTRL1000);
1146 if (unlikely(err < 0))
1147 return err;
1148 ctrl1000 = err;
1150 err = mii_read(np, np->phy_addr, MII_STAT1000);
1151 if (unlikely(err < 0))
1152 return err;
1153 stat1000 = err;
1231 int err, link_up;
1239 err = mii_read(np, np->phy_addr, MII_BMSR);
1240 if (err < 0)
1243 bmsr = err;
1251 err = 0;
1257 return err;
1264 int err;
1268 err = link_status_mii(np, link_up_p);
1273 return err;
1278 int err, limit;
1280 err = mdio_read(np, np->phy_addr,
1282 if (err < 0 || err == 0xffff)
1283 return err;
1284 err |= BMCR_RESET;
1285 err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1286 MII_BMCR, err);
1287 if (err)
1288 return err;
1292 err = mdio_read(np, np->phy_addr,
1294 if (err < 0)
1295 return err;
1296 if (!(err & BMCR_RESET))
1301 np->port, (err & 0xffff));
1312 int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1313 if (err < 0)
1314 return err;
1315 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1316 if (err < 0)
1317 return err;
1323 int err;
1326 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1328 if (err < 0)
1329 return err;
1330 err &= ~USER_ODIG_CTRL_GPIOS;
1331 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1332 err |= USER_ODIG_CTRL_RESV2;
1333 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1334 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1335 if (err)
1336 return err;
1345 int err;
1347 err = mdio_write(np, np->phy_addr,
1358 if (err)
1359 return err;
1361 err = mdio_write(np, np->phy_addr,
1367 if (err)
1368 return err;
1370 err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
1371 if (err)
1372 return err;
1373 err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
1374 if (err)
1375 return err;
1377 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1379 if (err < 0)
1380 return err;
1381 err &= ~USER_ODIG_CTRL_GPIOS;
1382 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1383 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1384 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1385 if (err)
1386 return err;
1395 int err;
1397 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1399 if (err < 0)
1400 return err;
1402 err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK);
1403 err |= MRVL88X2011_LED(MRVL88X2011_LED_ACT,val);
1406 MRVL88X2011_LED_8_TO_11_CTL, err);
1411 int err;
1413 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1415 if (err >= 0) {
1416 err &= ~MRVL88X2011_LED_BLKRATE_MASK;
1417 err |= (rate << 4);
1419 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1420 MRVL88X2011_LED_BLINK_CTL, err);
1423 return err;
1428 int err;
1431 err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS);
1432 if (err)
1433 return err;
1436 err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF);
1437 if (err)
1438 return err;
1440 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1442 if (err < 0)
1443 return err;
1445 err |= MRVL88X2011_ENA_XFPREFCLK;
1447 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1448 MRVL88X2011_GENERAL_CTL, err);
1449 if (err < 0)
1450 return err;
1452 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1454 if (err < 0)
1455 return err;
1458 err |= MRVL88X2011_LOOPBACK;
1460 err &= ~MRVL88X2011_LOOPBACK;
1462 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1463 MRVL88X2011_PMA_PMD_CTL_1, err);
1464 if (err < 0)
1465 return err;
1476 int err = 0;
1479 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1481 if (err < 0)
1482 return err;
1483 pr_info("Port %u PMA_PMD(MII_STAT1000) [%04x]\n", np->port, err);
1485 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
1486 if (err < 0)
1487 return err;
1488 pr_info("Port %u USER_DEV3(0x20) [%04x]\n", np->port, err);
1490 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1492 if (err < 0)
1493 return err;
1494 pr_info("Port %u PHYXS(MII_NWAYTEST) [%04x]\n", np->port, err);
1498 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1500 if (err < 0)
1501 return err;
1502 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1504 if (err < 0)
1505 return err;
1506 analog_stat0 = err;
1508 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1510 if (err < 0)
1511 return err;
1512 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1514 if (err < 0)
1515 return err;
1516 tx_alarm_status = err;
1534 int err;
1536 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1538 if (err < 0)
1539 return err;
1541 err &= ~BMCR_LOOPBACK;
1544 err |= BMCR_LOOPBACK;
1546 err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1547 MII_BMCR, err);
1548 if (err)
1549 return err;
1556 int err = 0;
1561 return err;
1572 err = bcm8704_reset(np);
1573 if (err)
1574 return err;
1576 err = xcvr_10g_set_lb_bcm870x(np);
1577 if (err)
1578 return err;
1580 err = bcm8706_init_user_dev3(np);
1581 if (err)
1582 return err;
1584 err = xcvr_diag_bcm870x(np);
1585 if (err)
1586 return err;
1593 int err;
1595 err = bcm8704_reset(np);
1596 if (err)
1597 return err;
1599 err = bcm8704_init_user_dev3(np);
1600 if (err)
1601 return err;
1603 err = xcvr_10g_set_lb_bcm870x(np);
1604 if (err)
1605 return err;
1607 err = xcvr_diag_bcm870x(np);
1608 if (err)
1609 return err;
1616 int phy_id, err;
1635 err = xcvr_init_10g_mrvl88x2011(np);
1639 err = xcvr_init_10g_bcm8704(np);
1643 return err;
1648 int limit, err;
1650 err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
1651 if (err)
1652 return err;
1657 err = mii_read(np, np->phy_addr, MII_BMCR);
1658 if (err < 0)
1659 return err;
1660 if (!(err & BMCR_RESET))
1665 np->port, err);
1674 int err;
1682 err = mii_reset(np);
1683 if (err)
1684 return err;
1686 err = mii_read(np, np->phy_addr, MII_BMSR);
1687 if (err < 0)
1688 return err;
1689 bmsr = err;
1693 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1694 if (err < 0)
1695 return err;
1696 estat = err;
1700 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1701 if (err)
1702 return err;
1709 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1710 if (err)
1711 return err;
1716 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1717 if (err)
1718 return err;
1720 err = mii_read(np, np->phy_addr, MII_BMCR);
1721 if (err < 0)
1722 return err;
1725 err = mii_read(np, np->phy_addr, MII_BMSR);
1726 if (err < 0)
1727 return err;
1736 int err;
1738 err = mii_reset(np);
1739 if (err)
1740 return err;
1742 err = mii_read(np, np->phy_addr, MII_BMSR);
1743 if (err < 0)
1744 return err;
1745 bmsr = err;
1749 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1750 if (err < 0)
1751 return err;
1752 estat = err;
1756 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1757 if (err)
1758 return err;
1773 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
1774 if (err)
1775 return err;
1794 err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
1795 if (err)
1796 return err;
1806 err = mii_write(np, np->phy_addr,
1808 if (err)
1809 return err;
1845 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1846 if (err)
1847 return err;
1850 err = mii_read(np, np->phy_addr, MII_BMCR);
1851 if (err < 0)
1852 return err;
1853 bmcr = err;
1855 err = mii_read(np, np->phy_addr, MII_BMSR);
1856 if (err < 0)
1857 return err;
1858 bmsr = err;
1882 int err;
1884 err = 0;
1886 err = ops->xcvr_init(np);
1888 return err;
1894 int err;
1896 err = 0;
1898 err = ops->serdes_init(np);
1900 return err;
1939 int err, link_up, pma_status, pcs_status;
1943 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1945 if (err < 0)
1949 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1951 if (err < 0)
1954 pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1957 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1959 if (err < 0)
1962 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1964 if (err < 0)
1967 pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1970 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR,
1972 if (err < 0)
1975 if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 |
1983 err = 0;
1990 return err;
1995 int err, link_up;
1998 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2000 if (err < 0 || err == 0xffff)
2002 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2003 err = 0;
2007 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2009 if (err < 0)
2012 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2013 err = 0;
2017 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2019 if (err < 0)
2021 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2028 err = 0;
2037 err = 0;
2041 return err;
2046 int err, link_up;
2050 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2052 if (err < 0)
2054 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2055 err = 0;
2059 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2061 if (err < 0)
2063 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2064 err = 0;
2068 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2070 if (err < 0)
2073 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2079 err = 0;
2086 err = 0;
2090 return err;
2096 int err = -EINVAL;
2109 err = link_status_10g_mrvl(np, link_up_p);
2113 err = link_status_10g_bcom(np, link_up_p);
2120 return err;
2163 int err = 0;
2179 err = np->phy_ops->xcvr_init(np);
2180 if (err) {
2181 err = mdio_read(np, np->phy_addr,
2183 if (err == 0xffff) {
2199 err = link_status_10g_bcm8706(np, link_up_p);
2200 if (err == 0xffff) {
2217 int err;
2219 err = 0;
2221 err = ops->link_status(np, link_up_p);
2223 return err;
2230 int err, link_up;
2232 err = niu_link_status(np, &link_up);
2233 if (!err)
2423 int err;
2425 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
2426 if (err)
2427 return err;
2428 err = esr_read_glue0(np, i, &glue0);
2429 if (err)
2430 return err;
2445 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
2446 if (err)
2447 return err;
2448 err = esr_write_glue0(np, i, glue0);
2449 if (err)
2450 return err;
2483 int err;
2484 err = serdes_init_1g_serdes(np);
2485 if (!err) {
2607 int err, ignore;
2610 err = niu_xcvr_init(np);
2611 if (err)
2612 return err;
2615 err = niu_serdes_init(np);
2616 if (err && !(np->flags & NIU_FLAGS_HOTPLUG_PHY))
2617 return err;
2619 err = niu_xcvr_init(np);
2620 if (!err || (np->flags & NIU_FLAGS_HOTPLUG_PHY))
2820 int err;
2823 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2824 if (!err) {
2834 return err;
2857 int err;
2860 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2861 if (!err)
2864 return err;
2998 int err;
3005 err = tcam_user_eth_class_enable(np, i, 0);
3006 if (err)
3007 return err;
3010 err = tcam_user_ip_class_enable(np, i, 0);
3011 if (err)
3012 return err;
3023 int err = tcam_flush(np, i);
3024 if (err)
3025 return err;
3133 int err = fflp_set_partition(np, 0, 0, 0, 0);
3134 if (err)
3135 return err;
3172 int err = hash_write(np, 0, i, 1, (u64 *) &ent);
3173 if (err)
3174 return err;
3183 int err;
3188 err = 0;
3193 err = fflp_disable_all_partitions(np);
3194 if (err) {
3196 "fflp_disable_all_partitions failed, err=%d\n",
3197 err);
3202 err = tcam_early_init(np);
3203 if (err) {
3205 "tcam_early_init failed, err=%d\n", err);
3213 err = tcam_flush_all(np);
3214 if (err) {
3216 "tcam_flush_all failed, err=%d\n", err);
3220 err = fflp_hash_clear(np);
3221 if (err) {
3223 "fflp_hash_clear failed, err=%d\n",
3224 err);
3235 return err;
3364 int err = niu_rbr_add_page(np, rp, mask, index);
3366 if (unlikely(err)) {
3516 int err, index = rp->rbr_index;
3518 err = 0;
3520 err = niu_rbr_add_page(np, rp, mask, index);
3521 if (unlikely(err))
3528 return err;
3836 int err = 0;
3841 err = -EINVAL;
3843 if (err) {
3854 return err;
4081 int i, err = 0;
4096 err = r;
4114 err = r;
4121 err = r;
4127 err = r;
4132 err = r;
4136 if (err)
4139 return err;
4241 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);
4242 if (err)
4476 int i, port, err;
4490 err = -ENOMEM;
4506 err = niu_alloc_rx_ring_info(np, rp);
4507 if (err)
4523 err = niu_rbr_fill(np, rp, GFP_KERNEL);
4524 if (err)
4530 err = -ENOMEM;
4546 err = niu_alloc_tx_ring_info(np, rp);
4547 if (err)
4555 return err;
4595 int err;
4600 err = niu_tx_cs_reset_poll(np, channel);
4601 if (!err)
4604 return err;
4674 int err, channel = rp->tx_channel;
4677 err = niu_tx_channel_stop(np, channel);
4678 if (err)
4679 return err;
4681 err = niu_tx_channel_reset(np, channel);
4682 if (err)
4683 return err;
4685 err = niu_tx_channel_lpage_init(np, channel);
4686 if (err)
4687 return err;
4766 int i, err, num_alt = niu_num_alt_addr(np);
4769 err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4770 if (err)
4771 return err;
4773 err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4774 if (err)
4775 return err;
4778 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
4779 if (err)
4780 return err;
4927 int err, channel = rp->rx_channel;
4930 err = niu_rx_channel_reset(np, channel);
4931 if (err)
4932 return err;
4934 err = niu_rx_channel_lpage_init(np, channel);
4935 if (err)
4936 return err;
4953 err = niu_compute_rbr_cfig_b(rp, &val);
4954 if (err)
4955 return err;
4965 err = niu_enable_rx_channel(np, channel, 1);
4966 if (err)
4967 return err;
4982 int err, i;
4994 err = niu_init_hostinfo(np);
4995 if (err)
4996 return err;
5001 err = niu_init_one_rx_channel(np, rp);
5002 if (err)
5003 return err;
5014 int index, err;
5027 err = tcam_write(np, index, tp->key, tp->key_mask);
5028 if (err)
5029 return err;
5030 err = tcam_assoc_write(np, index, tp->assoc_data);
5031 if (err)
5032 return err;
5043 int i, err;
5048 err = niu_init_hostinfo(np);
5049 if (err)
5050 return err;
5062 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
5064 if (err)
5065 return err;
5071 err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
5072 if (err)
5073 return err;
5074 err = niu_set_flow_key(np, i, parent->flow_key[index]);
5075 if (err)
5076 return err;
5079 err = niu_set_ip_frag_rule(np);
5080 if (err)
5081 return err;
5107 int err;
5109 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5111 if (err) {
5114 return err;
5122 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5124 if (err) {
5127 return err;
5154 int i, max, err;
5171 err = niu_zcp_write(np, i, data);
5172 if (err)
5173 return err;
5174 err = niu_zcp_read(np, i, rbuf);
5175 if (err)
5176 return err;
5221 int i, max, err;
5245 err = niu_ipp_reset(np);
5246 if (err)
5247 return err;
5809 int err;
5812 err = niu_init_pcs(np);
5813 if (err)
5814 return err;
5816 err = niu_reset_tx_mac(np);
5817 if (err)
5818 return err;
5820 err = niu_reset_rx_mac(np);
5821 if (err)
5822 return err;
5938 int i, err;
5949 err = niu_init_one_tx_channel(np, rp);
5950 if (err)
5951 return err;
5955 err = niu_init_rx_channels(np);
5956 if (err)
5960 err = niu_init_classifier_hw(np);
5961 if (err)
5965 err = niu_init_zcp(np);
5966 if (err)
5970 err = niu_init_ipp(np);
5971 if (err)
5975 err = niu_init_mac(np);
5976 if (err)
5995 return err;
6047 int i, j, err;
6051 err = 0;
6055 err = request_irq(lp->irq, niu_interrupt, IRQF_SHARED,
6057 if (err)
6070 return err;
6103 int err;
6107 err = niu_alloc_channels(np);
6108 if (err)
6111 err = niu_enable_interrupts(np, 0);
6112 if (err)
6115 err = niu_request_irq(np);
6116 if (err)
6123 err = niu_init_hw(np);
6124 if (!err) {
6128 err = niu_enable_interrupts(np, 1);
6129 if (err)
6135 if (err) {
6156 return err;
6332 int i, alt_cnt, err;
6356 err = niu_set_alt_mac(np, index, ha->addr);
6357 if (err)
6359 err, index);
6360 err = niu_enable_alt_mac(np, index, 1);
6361 if (err)
6363 err, index);
6374 err = niu_enable_alt_mac(np, i, 0);
6375 if (err)
6377 err, i);
6451 int i, j, k, err;
6470 err = niu_rbr_add_page(np, rp, GFP_ATOMIC, k);
6471 if (unlikely(err))
6502 int err;
6526 err = niu_init_hw(np);
6527 if (!err) {
6749 int err, orig_jumbo, new_jumbo;
6766 err = niu_alloc_channels(np);
6767 if (err)
6768 return err;
6772 err = niu_init_hw(np);
6773 if (!err) {
6777 err = niu_enable_interrupts(np, 1);
6778 if (err)
6784 if (!err) {
6792 return err;
7438 int err, ret;
7566 err = tcam_write(np, idx, tp->key, tp->key_mask);
7567 if (err) {
7571 err = tcam_assoc_write(np, idx, tp->assoc_data);
7572 if (err) {
8009 int err = niu_pci_eeprom_read(np, off);
8012 if (err < 0)
8013 return err;
8014 val = (err << 8);
8015 err = niu_pci_eeprom_read(np, off + 1);
8016 if (err < 0)
8017 return err;
8018 val |= (err & 0xff);
8025 int err = niu_pci_eeprom_read(np, off);
8028 if (err < 0)
8029 return err;
8031 val = (err & 0xff);
8032 err = niu_pci_eeprom_read(np, off + 1);
8033 if (err < 0)
8034 return err;
8036 val |= (err & 0xff) << 8;
8047 int err = niu_pci_eeprom_read(np, off + i);
8048 if (err < 0)
8049 return err;
8050 *namebuf++ = err;
8051 if (!err)
8101 int len, err, prop_len;
8111 err = niu_pci_eeprom_read(np, start + 2);
8112 if (err < 0)
8113 return err;
8114 len = err;
8120 err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64);
8121 if (err < 0)
8122 return err;
8158 u32 off = start + 5 + err;
8165 err = niu_pci_eeprom_read(np, off + i);
8166 if (err < 0)
8167 return err;
8168 *prop_buf++ = err;
8182 int err;
8184 err = niu_pci_eeprom_read16_swp(np, start + 1);
8185 if (err < 0)
8186 return err;
8188 offset = err + 3;
8194 err = niu_pci_eeprom_read(np, here);
8195 if (err < 0)
8196 return err;
8197 if (err != 0x90)
8200 err = niu_pci_eeprom_read16_swp(np, here + 1);
8201 if (err < 0)
8202 return err;
8205 end = start + offset + err;
8207 offset += err;
8209 err = niu_pci_vpd_scan_props(np, here, end);
8210 if (err < 0)
8211 return err;
8213 if (err == 1)
8223 int err;
8229 err = niu_pci_eeprom_read16(np, start + 0);
8230 if (err != 0x55aa)
8234 err = niu_pci_eeprom_read16(np, start + 23);
8235 if (err < 0)
8237 start += err;
8240 err = niu_pci_eeprom_read16(np, start + 0);
8241 if (err != 0x5043)
8243 err = niu_pci_eeprom_read16(np, start + 2);
8244 if (err != 0x4952)
8248 err = niu_pci_eeprom_read(np, start + 20);
8249 if (err < 0)
8251 if (err != 0x01) {
8252 err = niu_pci_eeprom_read(np, ret + 2);
8253 if (err < 0)
8256 start = ret + (err * 512);
8260 err = niu_pci_eeprom_read16_swp(np, start + 8);
8261 if (err < 0)
8262 return err;
8263 ret += err;
8265 err = niu_pci_eeprom_read(np, ret + 0);
8266 if (err != 0x82)
8775 int port, err;
8781 err = 0;
8789 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8791 if (err)
8797 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8799 if (err)
8803 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8805 if (err)
8810 return err;
8819 int err;
8850 err = fill_phy_probe_info(np, parent, info);
8851 if (err)
8852 return err;
8945 int err, i;
8948 err = walk_phys(np, parent);
8949 if (err)
8950 return err;
9102 int i, err, ldg_rotor;
9108 err = niu_n2_irq_init(np, ldg_num_map);
9109 if (err)
9110 return err;
9129 err = niu_set_ldg_sid(np, lp->ldg_num, port, i);
9130 if (err)
9131 return err;
9148 err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor],
9150 if (err)
9151 return err;
9158 err = niu_ldg_assign_ldn(np, parent,
9161 if (err)
9162 return err;
9168 err = niu_ldg_assign_ldn(np, parent,
9171 if (err)
9172 return err;
9186 err = niu_ldg_assign_ldn(np, parent,
9189 if (err)
9190 return err;
9201 err = niu_ldg_assign_ldn(np, parent,
9204 if (err)
9205 return err;
9287 int err, have_props;
9290 err = niu_get_of_props(np);
9291 if (err == -ENODEV)
9292 return err;
9294 have_props = !err;
9296 err = niu_init_mac_ipp_pcs_base(np);
9297 if (err)
9298 return err;
9301 err = niu_get_and_validate_port(np);
9302 if (err)
9303 return err;
9314 err = niu_pci_vpd_fetch(np, offset);
9315 if (err < 0)
9316 return err;
9322 err = niu_get_and_validate_port(np);
9323 if (err)
9324 return err;
9328 err = niu_get_and_validate_port(np);
9329 if (err)
9330 return err;
9331 err = niu_pci_probe_sprom(np);
9332 if (err)
9333 return err;
9337 err = niu_probe_ports(np);
9338 if (err)
9339 return err;
9346 err = niu_determine_phy_disposition(np);
9347 if (!err)
9348 err = niu_init_link(np);
9350 return err;
9480 int err = device_create_file(&plat_dev->dev,
9482 if (err)
9550 int err;
9553 err = sysfs_create_link(&p->plat_dev->dev.kobj,
9556 if (!err) {
9748 int err;
9752 err = pci_enable_device(pdev);
9753 if (err) {
9755 return err;
9761 err = -ENODEV;
9765 err = pci_request_regions(pdev, DRV_MODULE_NAME);
9766 if (err) {
9773 err = -ENODEV;
9780 err = -ENOMEM;
9793 err = -ENOMEM;
9803 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
9804 if (!err)
9806 if (err) {
9807 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9808 if (err) {
9821 err = -ENOMEM;
9836 err = niu_get_invariants(np);
9837 if (err) {
9838 if (err != -ENODEV)
9843 err = register_netdev(dev);
9844 if (err) {
9873 return err;
9931 int err;
9940 err = niu_init_hw(np);
9941 if (!err) {
9949 return err;
10027 int err;
10041 err = -ENOMEM;
10052 err = -ENOMEM;
10063 err = -ENOMEM;
10072 err = -ENOMEM;
10081 err = -ENOMEM;
10087 err = niu_get_invariants(np);
10088 if (err) {
10089 if (err != -ENODEV)
10094 err = register_netdev(dev);
10095 if (err) {
10132 return err;
10193 int err = 0;
10203 err = platform_driver_register(&niu_of_driver);
10206 if (!err) {
10207 err = pci_register_driver(&niu_pci_driver);
10209 if (err)
10214 return err;