Lines Matching defs:mask
128 #define INTR_TX_COMP_3_MASK 0xFFF80000 /* mask for TX completion
141 #define REG_INTR_MASK 0x0010 /* Interrupt mask */
147 #define REG_ALIAS_CLEAR 0x0014 /* alias clear mask
171 /* mask for PCI status events that will set PCI_ERR_STATUS. if cleared, event
175 #define REG_PCI_ERR_STATUS_MASK 0x1004 /* PCI Error status mask */
359 #define REG_PLUS_INTR_MASK_1 0x1038 /* Cassini+: interrupt mask
384 #define REG_PLUS_ALIAS_CLEAR_1 0x1040 /* Cassini+: alias clear mask
1018 #define RX_TABLE_ADDR_MASK 0x0000003F /* address mask */
1082 #define HP_INSTR_RAM_ADDR_MASK 0x01F /* 5-bit mask */
1178 #define HP_STATUS2_DATA_MASK_ZERO 0x00000100 /* mask of data length
1182 #define HP_STATUS2_MASK_TCP_THRESH 0x00000040 /* mask of payload
1244 * is read and have corresponding mask bits in mask register. events will
1245 * trigger an interrupt if the corresponding mask bit is 0.
1247 * mask register default = 0xFFFFFFFF on reset
1309 #define REG_MAC_TX_MASK 0x6020 /* TX MAC mask reg */
1311 #define REG_MAC_RX_MASK 0x6024 /* RX MAC mask reg */
1313 #define REG_MAC_CTRL_MASK 0x6028 /* MAC control mask reg */
1580 mask reg. 8-bit reg
1581 contains nibble mask for
1583 #define REG_MAC_ADDR_FILTER0_MASK 0x615C /* address filter 0 mask
1758 * the MIF_STATUS register will cause an interrupt. if a mask bit is 0,
1762 #define REG_MIF_MASK 0x6214 /* MIF mask reg */
2122 u16 mask, val;