Lines Matching defs:stat
981 u32 stat, state_machine;
988 stat = readl(cp->regs + REG_PCS_MII_STATUS);
989 if ((stat & PCS_MII_STATUS_LINK_STATUS) == 0)
990 stat = readl(cp->regs + REG_PCS_MII_STATUS);
995 if ((stat & (PCS_MII_STATUS_AUTONEG_COMP |
1005 stat &= ~PCS_MII_STATUS_LINK_STATUS;
1007 stat |= PCS_MII_STATUS_LINK_STATUS;
1010 if (stat & PCS_MII_STATUS_LINK_STATUS) {
1058 stat = readl(cp->regs + REG_PCS_SERDES_STATE);
1059 if (stat == 0x03)
1086 u32 stat = readl(cp->regs + REG_PCS_INTR_STATUS);
1088 if ((stat & PCS_INTR_STATUS_LINK_CHANGE) == 0)
1483 u32 stat = readl(cp->regs + REG_MAC_RX_STATUS);
1485 if (!stat)
1488 netif_dbg(cp, intr, cp->dev, "rxmac interrupt, stat: 0x%x\n", stat);
1492 if (stat & MAC_RX_ALIGN_ERR)
1495 if (stat & MAC_RX_CRC_ERR)
1498 if (stat & MAC_RX_LEN_ERR)
1501 if (stat & MAC_RX_OVERFLOW) {
1516 u32 stat = readl(cp->regs + REG_MAC_CTRL_STATUS);
1518 if (!stat)
1522 "mac interrupt, stat: 0x%x\n", stat);
1528 if (stat & MAC_CTRL_PAUSE_STATE)
1531 if (stat & MAC_CTRL_PAUSE_RECEIVED)
1532 cp->pause_last_time_recvd = (stat >> 16);
1656 u32 stat = readl(cp->regs + REG_MIF_STATUS);
1660 if (CAS_VAL(MIF_STATUS_POLL_STATUS, stat) == 0)
1663 bmsr = CAS_VAL(MIF_STATUS_POLL_DATA, stat);
1670 u32 stat = readl(cp->regs + REG_PCI_ERR_STATUS);
1672 if (!stat)
1676 stat, readl(cp->regs + REG_BIM_DIAG));
1679 if ((stat & PCI_ERR_BADACK) &&
1683 if (stat & PCI_ERR_DTRTO)
1685 if (stat & PCI_ERR_OTHER)
1687 if (stat & PCI_ERR_BIM_DMA_WRITE)
1689 if (stat & PCI_ERR_BIM_DMA_READ)
1693 if (stat & PCI_ERR_OTHER) {