Lines Matching defs:dwmac
3 * dwmac-stm32.c - DWMAC Specific Glue layer for STM32 MCU
101 int (*clk_prepare)(struct stm32_dwmac *dwmac, bool prepare);
102 int (*suspend)(struct stm32_dwmac *dwmac);
103 void (*resume)(struct stm32_dwmac *dwmac);
104 int (*parse_data)(struct stm32_dwmac *dwmac,
112 struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
115 if (dwmac->ops->set_mode) {
116 ret = dwmac->ops->set_mode(plat_dat);
121 ret = clk_prepare_enable(dwmac->clk_tx);
125 if (!dwmac->ops->clk_rx_enable_in_suspend ||
126 !dwmac->dev->power.is_suspended) {
127 ret = clk_prepare_enable(dwmac->clk_rx);
129 clk_disable_unprepare(dwmac->clk_tx);
134 if (dwmac->ops->clk_prepare) {
135 ret = dwmac->ops->clk_prepare(dwmac, true);
137 clk_disable_unprepare(dwmac->clk_rx);
138 clk_disable_unprepare(dwmac->clk_tx);
145 static int stm32mp1_clk_prepare(struct stm32_dwmac *dwmac, bool prepare)
150 ret = clk_prepare_enable(dwmac->syscfg_clk);
153 if (dwmac->enable_eth_ck) {
154 ret = clk_prepare_enable(dwmac->clk_eth_ck);
156 clk_disable_unprepare(dwmac->syscfg_clk);
161 clk_disable_unprepare(dwmac->syscfg_clk);
162 if (dwmac->enable_eth_ck)
163 clk_disable_unprepare(dwmac->clk_eth_ck);
170 struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
171 u32 reg = dwmac->mode_reg, clk_rate;
174 clk_rate = clk_get_rate(dwmac->clk_eth_ck);
175 dwmac->enable_eth_ck = false;
178 if (clk_rate == ETH_CK_F_25M && dwmac->ext_phyclk)
179 dwmac->enable_eth_ck = true;
186 (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk)) {
187 dwmac->enable_eth_ck = true;
195 (dwmac->eth_ref_clk_sel_reg || dwmac->ext_phyclk)) {
196 dwmac->enable_eth_ck = true;
207 (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk)) {
208 dwmac->enable_eth_ck = true;
221 regmap_write(dwmac->regmap, reg + SYSCFG_PMCCLRR_OFFSET,
222 dwmac->ops->syscfg_eth_mask);
225 return regmap_update_bits(dwmac->regmap, reg,
226 dwmac->ops->syscfg_eth_mask, val);
231 struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
232 u32 reg = dwmac->mode_reg;
251 return regmap_update_bits(dwmac->regmap, reg,
252 dwmac->ops->syscfg_eth_mask, val << 23);
255 static void stm32_dwmac_clk_disable(struct stm32_dwmac *dwmac)
257 clk_disable_unprepare(dwmac->clk_tx);
258 clk_disable_unprepare(dwmac->clk_rx);
260 if (dwmac->ops->clk_prepare)
261 dwmac->ops->clk_prepare(dwmac, false);
264 static int stm32_dwmac_parse_data(struct stm32_dwmac *dwmac,
271 dwmac->clk_tx = devm_clk_get(dev, "mac-clk-tx");
272 if (IS_ERR(dwmac->clk_tx)) {
274 return PTR_ERR(dwmac->clk_tx);
277 dwmac->clk_rx = devm_clk_get(dev, "mac-clk-rx");
278 if (IS_ERR(dwmac->clk_rx)) {
280 return PTR_ERR(dwmac->clk_rx);
283 if (dwmac->ops->parse_data) {
284 err = dwmac->ops->parse_data(dwmac, dev);
290 dwmac->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscon");
291 if (IS_ERR(dwmac->regmap))
292 return PTR_ERR(dwmac->regmap);
294 err = of_property_read_u32_index(np, "st,syscon", 1, &dwmac->mode_reg);
301 static int stm32mp1_parse_data(struct stm32_dwmac *dwmac,
309 dwmac->ext_phyclk = of_property_read_bool(np, "st,ext-phyclk");
312 dwmac->eth_clk_sel_reg = of_property_read_bool(np, "st,eth-clk-sel");
315 dwmac->eth_ref_clk_sel_reg =
319 dwmac->clk_eth_ck = devm_clk_get(dev, "eth-ck");
320 if (IS_ERR(dwmac->clk_eth_ck)) {
322 dwmac->clk_eth_ck = NULL;
326 dwmac->clk_ethstp = devm_clk_get(dev, "ethstp");
327 if (IS_ERR(dwmac->clk_ethstp)) {
330 return PTR_ERR(dwmac->clk_ethstp);
334 dwmac->syscfg_clk = devm_clk_get(dev, "syscfg-clk");
335 if (IS_ERR(dwmac->syscfg_clk))
336 dwmac->syscfg_clk = NULL;
341 dwmac->irq_pwr_wakeup = platform_get_irq_byname_optional(pdev,
343 if (dwmac->irq_pwr_wakeup == -EPROBE_DEFER)
346 if (!dwmac->clk_eth_ck && dwmac->irq_pwr_wakeup >= 0) {
353 dwmac->irq_pwr_wakeup);
367 struct stm32_dwmac *dwmac;
379 dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL);
380 if (!dwmac) {
392 dwmac->ops = data;
393 dwmac->dev = &pdev->dev;
395 ret = stm32_dwmac_parse_data(dwmac, &pdev->dev);
401 plat_dat->bsp_priv = dwmac;
414 stm32_dwmac_clk_disable(dwmac);
425 struct stm32_dwmac *dwmac = priv->plat->bsp_priv;
431 if (dwmac->irq_pwr_wakeup >= 0) {
437 static int stm32mp1_suspend(struct stm32_dwmac *dwmac)
441 ret = clk_prepare_enable(dwmac->clk_ethstp);
445 clk_disable_unprepare(dwmac->clk_tx);
446 clk_disable_unprepare(dwmac->syscfg_clk);
447 if (dwmac->enable_eth_ck)
448 clk_disable_unprepare(dwmac->clk_eth_ck);
453 static void stm32mp1_resume(struct stm32_dwmac *dwmac)
455 clk_disable_unprepare(dwmac->clk_ethstp);
458 static int stm32mcu_suspend(struct stm32_dwmac *dwmac)
460 clk_disable_unprepare(dwmac->clk_tx);
461 clk_disable_unprepare(dwmac->clk_rx);
471 struct stm32_dwmac *dwmac = priv->plat->bsp_priv;
477 if (dwmac->ops->suspend)
478 ret = dwmac->ops->suspend(dwmac);
487 struct stm32_dwmac *dwmac = priv->plat->bsp_priv;
490 if (dwmac->ops->resume)
491 dwmac->ops->resume(dwmac);
523 { .compatible = "st,stm32-dwmac", .data = &stm32mcu_dwmac_data},
524 { .compatible = "st,stm32mp1-dwmac", .data = &stm32mp1_dwmac_data},
533 .name = "stm32-dwmac",