Lines Matching refs:ethqos
103 int (*configure_func)(struct qcom_ethqos *ethqos);
117 static int rgmii_readl(struct qcom_ethqos *ethqos, unsigned int offset)
119 return readl(ethqos->rgmii_base + offset);
122 static void rgmii_writel(struct qcom_ethqos *ethqos,
125 writel(value, ethqos->rgmii_base + offset);
128 static void rgmii_updatel(struct qcom_ethqos *ethqos,
133 temp = rgmii_readl(ethqos, offset);
135 rgmii_writel(ethqos, temp, offset);
140 struct qcom_ethqos *ethqos = priv;
141 struct device *dev = ðqos->pdev->dev;
145 rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG));
147 rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG));
149 rgmii_readl(ethqos, SDCC_HC_REG_DDR_CONFIG));
151 rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG2));
153 rgmii_readl(ethqos, SDC4_STATUS));
155 rgmii_readl(ethqos, SDCC_USR_CTL));
157 rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG2));
159 rgmii_readl(ethqos, RGMII_IO_MACRO_DEBUG1));
161 rgmii_readl(ethqos, EMAC_SYSTEM_LOW_POWER_DEBUG));
170 ethqos_update_link_clk(struct qcom_ethqos *ethqos, unsigned int speed)
174 ethqos->link_clk_rate = RGMII_1000_NOM_CLK_FREQ;
178 ethqos->link_clk_rate = RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ;
182 ethqos->link_clk_rate = RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ;
186 clk_set_rate(ethqos->link_clk, ethqos->link_clk_rate);
189 static void ethqos_set_func_clk_en(struct qcom_ethqos *ethqos)
191 rgmii_updatel(ethqos, RGMII_CONFIG_FUNC_CLK_EN,
293 static int ethqos_dll_configure(struct qcom_ethqos *ethqos)
295 struct device *dev = ðqos->pdev->dev;
300 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EN,
304 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EXT_EN,
308 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
312 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN,
315 if (!ethqos->has_emac_ge_3) {
316 rgmii_updatel(ethqos, SDCC_DLL_MCLK_GATING_EN,
319 rgmii_updatel(ethqos, SDCC_DLL_CDR_FINE_PHASE,
325 val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG);
336 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
342 val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG);
353 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_CAL_EN,
356 if (!ethqos->has_emac_ge_3) {
357 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DLL_CLOCK_DIS,
360 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_MCLK_FREQ_CALC,
363 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL,
366 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW,
374 static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos)
376 struct device *dev = ðqos->pdev->dev;
381 if (ethqos->phy_mode == PHY_INTERFACE_MODE_RGMII_ID ||
382 ethqos->phy_mode == PHY_INTERFACE_MODE_RGMII_TXID)
388 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN,
392 if (ethqos->rgmii_config_loopback_en)
398 rgmii_updatel(ethqos, RGMII_CONFIG_INTF_SEL,
401 switch (ethqos->speed) {
403 rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE,
405 rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
407 rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
410 rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP,
412 rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
415 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
417 rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
419 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
426 if (ethqos->has_emac_ge_3) {
428 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY,
432 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY,
435 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_DLY_EN,
438 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
443 rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE,
445 rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
448 rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
450 rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP,
452 rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
454 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
456 rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_2,
458 rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
461 if (ethqos->has_emac_ge_3)
462 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
466 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
470 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,
472 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
475 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
478 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
483 rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE,
485 rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
488 rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
490 rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP,
492 rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
494 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
496 rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_9,
499 rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
501 if (ethqos->has_emac_ge_3)
502 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
506 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
509 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,
511 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
514 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
517 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
521 dev_err(dev, "Invalid speed %d\n", ethqos->speed);
528 static int ethqos_configure_rgmii(struct qcom_ethqos *ethqos)
530 struct device *dev = ðqos->pdev->dev;
535 for (i = 0; i < ethqos->num_por; i++)
536 rgmii_writel(ethqos, ethqos->por[i].value,
537 ethqos->por[i].offset);
538 ethqos_set_func_clk_en(ethqos);
543 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST,
547 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN,
550 if (ethqos->has_emac_ge_3) {
551 if (ethqos->speed == SPEED_1000) {
552 rgmii_writel(ethqos, 0x1800000, SDCC_TEST_CTL);
553 rgmii_writel(ethqos, 0x2C010800, SDCC_USR_CTL);
554 rgmii_writel(ethqos, 0xA001, SDCC_HC_REG_DLL_CONFIG2);
556 rgmii_writel(ethqos, 0x40010800, SDCC_USR_CTL);
557 rgmii_writel(ethqos, 0xA001, SDCC_HC_REG_DLL_CONFIG2);
562 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST, 0,
566 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN, 0,
569 if (ethqos->speed != SPEED_100 && ethqos->speed != SPEED_10) {
571 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN,
575 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
580 if (!ethqos->has_emac_ge_3)
581 rgmii_updatel(ethqos, GENMASK(26, 24), BIT(26),
587 dll_lock = rgmii_readl(ethqos, SDC4_STATUS);
596 if (ethqos->speed == SPEED_1000)
597 ethqos_dll_configure(ethqos);
599 ethqos_rgmii_macro_init(ethqos);
607 static int ethqos_configure_sgmii(struct qcom_ethqos *ethqos)
611 val = readl(ethqos->mac_base + MAC_CTRL_REG);
613 switch (ethqos->speed) {
616 rgmii_updatel(ethqos, RGMII_CONFIG2_RGMII_CLK_SEL_CFG,
626 rgmii_updatel(ethqos, RGMII_CONFIG_SGMII_CLK_DVDR,
633 writel(val, ethqos->mac_base + MAC_CTRL_REG);
638 static int ethqos_configure(struct qcom_ethqos *ethqos)
640 return ethqos->configure_func(ethqos);
645 struct qcom_ethqos *ethqos = priv;
647 ethqos->speed = speed;
648 ethqos_update_link_clk(ethqos, speed);
649 ethqos_configure(ethqos);
654 struct qcom_ethqos *ethqos = priv;
657 ret = phy_init(ethqos->serdes_phy);
661 ret = phy_power_on(ethqos->serdes_phy);
665 return phy_set_speed(ethqos->serdes_phy, ethqos->speed);
670 struct qcom_ethqos *ethqos = priv;
672 phy_power_off(ethqos->serdes_phy);
673 phy_exit(ethqos->serdes_phy);
678 struct qcom_ethqos *ethqos = priv;
682 ret = clk_prepare_enable(ethqos->link_clk);
684 dev_err(ðqos->pdev->dev, "link_clk enable failed\n");
693 ethqos_set_func_clk_en(ethqos);
695 clk_disable_unprepare(ethqos->link_clk);
730 struct qcom_ethqos *ethqos;
746 ethqos = devm_kzalloc(dev, sizeof(*ethqos), GFP_KERNEL);
747 if (!ethqos)
750 ret = of_get_phy_mode(np, ðqos->phy_mode);
753 switch (ethqos->phy_mode) {
758 ethqos->configure_func = ethqos_configure_rgmii;
761 ethqos->configure_func = ethqos_configure_sgmii;
765 phy_modes(ethqos->phy_mode));
769 ethqos->pdev = pdev;
770 ethqos->rgmii_base = devm_platform_ioremap_resource_byname(pdev, "rgmii");
771 if (IS_ERR(ethqos->rgmii_base))
772 return dev_err_probe(dev, PTR_ERR(ethqos->rgmii_base),
775 ethqos->mac_base = stmmac_res.addr;
778 ethqos->por = data->por;
779 ethqos->num_por = data->num_por;
780 ethqos->rgmii_config_loopback_en = data->rgmii_config_loopback_en;
781 ethqos->has_emac_ge_3 = data->has_emac_ge_3;
783 ethqos->link_clk = devm_clk_get(dev, data->link_clk_name ?: "rgmii");
784 if (IS_ERR(ethqos->link_clk))
785 return dev_err_probe(dev, PTR_ERR(ethqos->link_clk),
788 ret = ethqos_clks_config(ethqos, true);
792 ret = devm_add_action_or_reset(dev, ethqos_clks_disable, ethqos);
796 ethqos->serdes_phy = devm_phy_optional_get(dev, "serdes");
797 if (IS_ERR(ethqos->serdes_phy))
798 return dev_err_probe(dev, PTR_ERR(ethqos->serdes_phy),
801 ethqos->speed = SPEED_1000;
802 ethqos_update_link_clk(ethqos, SPEED_1000);
803 ethqos_set_func_clk_en(ethqos);
805 plat_dat->bsp_priv = ethqos;
810 if (ethqos->has_emac_ge_3)
815 if (of_device_is_compatible(np, "qcom,qcs404-ethqos"))
820 if (ethqos->serdes_phy) {
829 { .compatible = "qcom,qcs404-ethqos", .data = &emac_v2_3_0_data},
830 { .compatible = "qcom,sa8775p-ethqos", .data = &emac_v4_0_0_data},
831 { .compatible = "qcom,sc8280xp-ethqos", .data = &emac_v3_0_0_data},
832 { .compatible = "qcom,sm8150-ethqos", .data = &emac_v2_1_0_data},
840 .name = "qcom-ethqos",