Lines Matching refs:plat
91 int (*dwmac_set_phy_interface)(struct mediatek_dwmac_plat_data *plat);
92 int (*dwmac_set_delay)(struct mediatek_dwmac_plat_data *plat);
112 static int mt2712_set_interface(struct mediatek_dwmac_plat_data *plat)
114 int rmii_clk_from_mac = plat->rmii_clk_from_mac ? RMII_CLK_SRC_INTERNAL : 0;
115 int rmii_rxc = plat->rmii_rxc ? RMII_CLK_SRC_RXC : 0;
119 switch (plat->phy_mode) {
133 dev_err(plat->dev, "phy interface not supported\n");
137 regmap_write(plat->peri_regmap, PERI_ETH_PHY_INTF_SEL, intf_val);
142 static void mt2712_delay_ps2stage(struct mediatek_dwmac_plat_data *plat)
144 struct mac_delay_struct *mac_delay = &plat->mac_delay;
146 switch (plat->phy_mode) {
162 dev_err(plat->dev, "phy interface not supported\n");
167 static void mt2712_delay_stage2ps(struct mediatek_dwmac_plat_data *plat)
169 struct mac_delay_struct *mac_delay = &plat->mac_delay;
171 switch (plat->phy_mode) {
187 dev_err(plat->dev, "phy interface not supported\n");
192 static int mt2712_set_delay(struct mediatek_dwmac_plat_data *plat)
194 struct mac_delay_struct *mac_delay = &plat->mac_delay;
197 mt2712_delay_ps2stage(plat);
199 switch (plat->phy_mode) {
210 if (plat->rmii_clk_from_mac) {
230 if (plat->rmii_rxc) {
270 dev_err(plat->dev, "phy interface not supported\n");
273 regmap_write(plat->peri_regmap, PERI_ETH_DLY, delay_val);
274 regmap_write(plat->peri_regmap, PERI_ETH_DLY_FINE, fine_val);
276 mt2712_delay_stage2ps(plat);
291 static int mt8195_set_interface(struct mediatek_dwmac_plat_data *plat)
293 int rmii_clk_from_mac = plat->rmii_clk_from_mac ? MT8195_RMII_CLK_SRC_INTERNAL : 0;
294 int rmii_rxc = plat->rmii_rxc ? MT8195_RMII_CLK_SRC_RXC : 0;
298 switch (plat->phy_mode) {
313 dev_err(plat->dev, "phy interface not supported\n");
320 regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL0, intf_val);
325 static void mt8195_delay_ps2stage(struct mediatek_dwmac_plat_data *plat)
327 struct mac_delay_struct *mac_delay = &plat->mac_delay;
334 static void mt8195_delay_stage2ps(struct mediatek_dwmac_plat_data *plat)
336 struct mac_delay_struct *mac_delay = &plat->mac_delay;
343 static int mt8195_set_delay(struct mediatek_dwmac_plat_data *plat)
345 struct mac_delay_struct *mac_delay = &plat->mac_delay;
348 mt8195_delay_ps2stage(plat);
350 switch (plat->phy_mode) {
361 if (plat->rmii_clk_from_mac) {
387 if (plat->rmii_rxc) {
426 dev_err(plat->dev, "phy interface not supported\n");
430 regmap_update_bits(plat->peri_regmap,
437 regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL1, delay_val);
438 regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL2, rmii_delay_val);
440 mt8195_delay_stage2ps(plat);
455 static int mediatek_dwmac_config_dt(struct mediatek_dwmac_plat_data *plat)
457 struct mac_delay_struct *mac_delay = &plat->mac_delay;
461 plat->peri_regmap = syscon_regmap_lookup_by_phandle(plat->np, "mediatek,pericfg");
462 if (IS_ERR(plat->peri_regmap)) {
463 dev_err(plat->dev, "Failed to get pericfg syscon\n");
464 return PTR_ERR(plat->peri_regmap);
467 err = of_get_phy_mode(plat->np, &plat->phy_mode);
469 dev_err(plat->dev, "not find phy-mode\n");
473 if (!of_property_read_u32(plat->np, "mediatek,tx-delay-ps", &tx_delay_ps)) {
474 if (tx_delay_ps < plat->variant->tx_delay_max) {
477 dev_err(plat->dev, "Invalid TX clock delay: %dps\n", tx_delay_ps);
482 if (!of_property_read_u32(plat->np, "mediatek,rx-delay-ps", &rx_delay_ps)) {
483 if (rx_delay_ps < plat->variant->rx_delay_max) {
486 dev_err(plat->dev, "Invalid RX clock delay: %dps\n", rx_delay_ps);
491 mac_delay->tx_inv = of_property_read_bool(plat->np, "mediatek,txc-inverse");
492 mac_delay->rx_inv = of_property_read_bool(plat->np, "mediatek,rxc-inverse");
493 plat->rmii_rxc = of_property_read_bool(plat->np, "mediatek,rmii-rxc");
494 plat->rmii_clk_from_mac = of_property_read_bool(plat->np, "mediatek,rmii-clk-from-mac");
495 plat->mac_wol = of_property_read_bool(plat->np, "mediatek,mac-wol");
500 static int mediatek_dwmac_clk_init(struct mediatek_dwmac_plat_data *plat)
502 const struct mediatek_dwmac_variant *variant = plat->variant;
505 plat->clks = devm_kcalloc(plat->dev, variant->num_clks, sizeof(*plat->clks), GFP_KERNEL);
506 if (!plat->clks)
510 plat->clks[i].id = variant->clk_list[i];
512 ret = devm_clk_bulk_get(plat->dev, variant->num_clks, plat->clks);
522 if (plat->rmii_clk_from_mac) {
523 plat->rmii_internal_clk = devm_clk_get(plat->dev, "rmii_internal");
524 if (IS_ERR(plat->rmii_internal_clk))
525 ret = PTR_ERR(plat->rmii_internal_clk);
527 plat->rmii_internal_clk = NULL;
535 struct mediatek_dwmac_plat_data *plat = priv;
536 const struct mediatek_dwmac_variant *variant = plat->variant;
540 ret = variant->dwmac_set_phy_interface(plat);
542 dev_err(plat->dev, "failed to set phy interface, err = %d\n", ret);
548 ret = variant->dwmac_set_delay(plat);
550 dev_err(plat->dev, "failed to set delay value, err = %d\n", ret);
560 struct mediatek_dwmac_plat_data *plat = priv;
561 const struct mediatek_dwmac_variant *variant = plat->variant;
565 ret = clk_bulk_prepare_enable(variant->num_clks, plat->clks);
567 dev_err(plat->dev, "failed to enable clks, err = %d\n", ret);
571 ret = clk_prepare_enable(plat->rmii_internal_clk);
573 dev_err(plat->dev, "failed to enable rmii internal clk, err = %d\n", ret);
577 clk_disable_unprepare(plat->rmii_internal_clk);
578 clk_bulk_disable_unprepare(variant->num_clks, plat->clks);
585 struct plat_stmmacenet_data *plat,
590 plat->mac_interface = priv_plat->phy_mode;
592 plat->flags |= STMMAC_FLAG_USE_PHY_WOL;
594 plat->flags &= ~STMMAC_FLAG_USE_PHY_WOL;
595 plat->riwt_off = 1;
596 plat->maxmtu = ETH_DATA_LEN;
597 plat->host_dma_width = priv_plat->variant->dma_bit_mask;
598 plat->bsp_priv = priv_plat;
599 plat->init = mediatek_dwmac_init;
600 plat->clks_config = mediatek_dwmac_clks_config;
602 plat->safety_feat_cfg = devm_kzalloc(&pdev->dev,
603 sizeof(*plat->safety_feat_cfg),
605 if (!plat->safety_feat_cfg)
608 plat->safety_feat_cfg->tsoee = 1;
609 plat->safety_feat_cfg->mrxpee = 0;
610 plat->safety_feat_cfg->mestee = 1;
611 plat->safety_feat_cfg->mrxee = 1;
612 plat->safety_feat_cfg->mtxee = 1;
613 plat->safety_feat_cfg->epsi = 0;
614 plat->safety_feat_cfg->edpp = 1;
615 plat->safety_feat_cfg->prtyen = 1;
616 plat->safety_feat_cfg->tmouten = 1;
618 for (i = 0; i < plat->tx_queues_to_use; i++) {
621 plat->tx_queues_cfg[i].tbs_en = 1;