Lines Matching refs:plat
35 int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat);
96 if (priv->plat->max_speed == 2500)
249 priv->plat->max_speed = 2500;
250 priv->plat->phy_interface = PHY_INTERFACE_MODE_2500BASEX;
251 priv->plat->mdio_bus_data->xpcs_an_inband = false;
253 priv->plat->max_speed = 1000;
265 intel_priv = (struct intel_priv_data *)priv->plat->bsp_priv;
323 intel_priv = priv->plat->bsp_priv;
328 if (priv->plat->flags & STMMAC_FLAG_EXT_SNAPSHOT_EN)
331 priv->plat->flags |= STMMAC_FLAG_INT_SNAPSHOT_EN;
337 switch (priv->plat->int_snapshot_num) {
352 priv->plat->flags &= ~STMMAC_FLAG_INT_SNAPSHOT_EN;
378 priv->plat->flags &= ~STMMAC_FLAG_INT_SNAPSHOT_EN;
397 priv->plat->flags &= ~STMMAC_FLAG_INT_SNAPSHOT_EN;
417 static void common_default_data(struct plat_stmmacenet_data *plat)
419 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */
420 plat->has_gmac = 1;
421 plat->force_sf_dma_mode = 1;
423 plat->mdio_bus_data->needs_reset = true;
426 plat->multicast_filter_bins = HASH_TABLE_SIZE;
429 plat->unicast_filter_entries = 1;
432 plat->maxmtu = JUMBO_LEN;
435 plat->tx_queues_to_use = 1;
436 plat->rx_queues_to_use = 1;
439 plat->tx_queues_cfg[0].use_prio = false;
440 plat->rx_queues_cfg[0].use_prio = false;
443 plat->rx_queues_cfg[0].pkt_route = 0x0;
447 struct plat_stmmacenet_data *plat)
454 plat->pdev = pdev;
455 plat->phy_addr = -1;
456 plat->clk_csr = 5;
457 plat->has_gmac = 0;
458 plat->has_gmac4 = 1;
459 plat->force_sf_dma_mode = 0;
460 plat->flags |= (STMMAC_FLAG_TSO_EN | STMMAC_FLAG_SPH_DISABLE);
471 plat->mult_fact_100ns = 1;
473 plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP;
475 for (i = 0; i < plat->rx_queues_to_use; i++) {
476 plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;
477 plat->rx_queues_cfg[i].chan = i;
480 plat->rx_queues_cfg[i].use_prio = false;
483 plat->rx_queues_cfg[i].pkt_route = 0x0;
486 for (i = 0; i < plat->tx_queues_to_use; i++) {
487 plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;
490 plat->tx_queues_cfg[i].use_prio = false;
493 plat->tx_queues_cfg[i].tbs_en = 1;
497 plat->tx_fifo_size = plat->tx_queues_to_use * 4096;
498 plat->rx_fifo_size = plat->rx_queues_to_use * 4096;
500 plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR;
501 plat->tx_queues_cfg[0].weight = 0x09;
502 plat->tx_queues_cfg[1].weight = 0x0A;
503 plat->tx_queues_cfg[2].weight = 0x0B;
504 plat->tx_queues_cfg[3].weight = 0x0C;
505 plat->tx_queues_cfg[4].weight = 0x0D;
506 plat->tx_queues_cfg[5].weight = 0x0E;
507 plat->tx_queues_cfg[6].weight = 0x0F;
508 plat->tx_queues_cfg[7].weight = 0x10;
510 plat->dma_cfg->pbl = 32;
511 plat->dma_cfg->pblx8 = true;
512 plat->dma_cfg->fixed_burst = 0;
513 plat->dma_cfg->mixed_burst = 0;
514 plat->dma_cfg->aal = 0;
515 plat->dma_cfg->dche = true;
517 plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi),
519 if (!plat->axi)
522 plat->axi->axi_lpi_en = 0;
523 plat->axi->axi_xit_frm = 0;
524 plat->axi->axi_wr_osr_lmt = 1;
525 plat->axi->axi_rd_osr_lmt = 1;
526 plat->axi->axi_blen[0] = 4;
527 plat->axi->axi_blen[1] = 8;
528 plat->axi->axi_blen[2] = 16;
530 plat->ptp_max_adj = plat->clk_ptp_rate;
531 plat->eee_usecs_rate = plat->clk_ptp_rate;
536 plat->stmmac_clk = clk_register_fixed_rate(&pdev->dev,
538 plat->clk_ptp_rate);
540 if (IS_ERR(plat->stmmac_clk)) {
542 plat->stmmac_clk = NULL;
545 ret = clk_prepare_enable(plat->stmmac_clk);
547 clk_unregister_fixed_rate(plat->stmmac_clk);
551 plat->ptp_clk_freq_config = intel_mgbe_ptp_clk_freq_config;
554 plat->multicast_filter_bins = HASH_TABLE_SIZE;
557 plat->unicast_filter_entries = 1;
560 plat->maxmtu = JUMBO_LEN;
562 plat->flags |= STMMAC_FLAG_VLAN_FAIL_Q_EN;
565 plat->vlan_fail_q = plat->rx_queues_to_use - 1;
579 plat->phy_interface = phy_mode;
586 if (plat->phy_interface == PHY_INTERFACE_MODE_SGMII ||
587 plat->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
588 plat->mdio_bus_data->has_xpcs = true;
589 plat->mdio_bus_data->xpcs_an_inband = true;
598 plat->mdio_bus_data->xpcs_an_inband = false;
604 plat->mdio_bus_data->phy_mask = 1 << INTEL_MGBE_ADHOC_ADDR;
605 plat->mdio_bus_data->phy_mask |= 1 << INTEL_MGBE_XPCS_ADDR;
607 plat->int_snapshot_num = AUX_SNAPSHOT1;
608 plat->ext_snapshot_num = AUX_SNAPSHOT0;
610 plat->crosststamp = intel_crosststamp;
611 plat->flags &= ~STMMAC_FLAG_INT_SNAPSHOT_EN;
614 plat->msi_mac_vec = 29;
615 plat->msi_lpi_vec = 28;
616 plat->msi_sfty_ce_vec = 27;
617 plat->msi_sfty_ue_vec = 26;
618 plat->msi_rx_base_vec = 0;
619 plat->msi_tx_base_vec = 1;
625 struct plat_stmmacenet_data *plat)
627 plat->rx_queues_to_use = 8;
628 plat->tx_queues_to_use = 8;
629 plat->flags |= STMMAC_FLAG_USE_PHY_WOL;
630 plat->flags |= STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY;
632 plat->safety_feat_cfg->tsoee = 1;
633 plat->safety_feat_cfg->mrxpee = 1;
634 plat->safety_feat_cfg->mestee = 1;
635 plat->safety_feat_cfg->mrxee = 1;
636 plat->safety_feat_cfg->mtxee = 1;
637 plat->safety_feat_cfg->epsi = 0;
638 plat->safety_feat_cfg->edpp = 0;
639 plat->safety_feat_cfg->prtyen = 0;
640 plat->safety_feat_cfg->tmouten = 0;
642 return intel_mgbe_common_data(pdev, plat);
646 struct plat_stmmacenet_data *plat)
648 plat->bus_id = 1;
649 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
650 plat->speed_mode_2500 = intel_speed_mode_2500;
651 plat->serdes_powerup = intel_serdes_powerup;
652 plat->serdes_powerdown = intel_serdes_powerdown;
654 plat->clk_ptp_rate = 204800000;
656 return ehl_common_data(pdev, plat);
664 struct plat_stmmacenet_data *plat)
666 plat->bus_id = 1;
667 plat->phy_interface = PHY_INTERFACE_MODE_RGMII;
669 plat->clk_ptp_rate = 204800000;
671 return ehl_common_data(pdev, plat);
679 struct plat_stmmacenet_data *plat)
681 struct intel_priv_data *intel_priv = plat->bsp_priv;
684 plat->bus_id = 2;
685 plat->host_dma_width = 32;
687 plat->clk_ptp_rate = 200000000;
691 return ehl_common_data(pdev, plat);
695 struct plat_stmmacenet_data *plat)
697 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID;
698 return ehl_pse0_common_data(pdev, plat);
706 struct plat_stmmacenet_data *plat)
708 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
709 plat->speed_mode_2500 = intel_speed_mode_2500;
710 plat->serdes_powerup = intel_serdes_powerup;
711 plat->serdes_powerdown = intel_serdes_powerdown;
712 return ehl_pse0_common_data(pdev, plat);
720 struct plat_stmmacenet_data *plat)
722 struct intel_priv_data *intel_priv = plat->bsp_priv;
725 plat->bus_id = 3;
726 plat->host_dma_width = 32;
728 plat->clk_ptp_rate = 200000000;
732 return ehl_common_data(pdev, plat);
736 struct plat_stmmacenet_data *plat)
738 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID;
739 return ehl_pse1_common_data(pdev, plat);
747 struct plat_stmmacenet_data *plat)
749 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
750 plat->speed_mode_2500 = intel_speed_mode_2500;
751 plat->serdes_powerup = intel_serdes_powerup;
752 plat->serdes_powerdown = intel_serdes_powerdown;
753 return ehl_pse1_common_data(pdev, plat);
761 struct plat_stmmacenet_data *plat)
763 plat->rx_queues_to_use = 6;
764 plat->tx_queues_to_use = 4;
765 plat->clk_ptp_rate = 204800000;
766 plat->speed_mode_2500 = intel_speed_mode_2500;
768 plat->safety_feat_cfg->tsoee = 1;
769 plat->safety_feat_cfg->mrxpee = 0;
770 plat->safety_feat_cfg->mestee = 1;
771 plat->safety_feat_cfg->mrxee = 1;
772 plat->safety_feat_cfg->mtxee = 1;
773 plat->safety_feat_cfg->epsi = 0;
774 plat->safety_feat_cfg->edpp = 0;
775 plat->safety_feat_cfg->prtyen = 0;
776 plat->safety_feat_cfg->tmouten = 0;
778 return intel_mgbe_common_data(pdev, plat);
782 struct plat_stmmacenet_data *plat)
784 plat->bus_id = 1;
785 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
786 plat->serdes_powerup = intel_serdes_powerup;
787 plat->serdes_powerdown = intel_serdes_powerdown;
788 return tgl_common_data(pdev, plat);
796 struct plat_stmmacenet_data *plat)
798 plat->bus_id = 2;
799 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
800 plat->serdes_powerup = intel_serdes_powerup;
801 plat->serdes_powerdown = intel_serdes_powerdown;
802 return tgl_common_data(pdev, plat);
810 struct plat_stmmacenet_data *plat)
812 plat->bus_id = 1;
813 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
817 return tgl_common_data(pdev, plat);
825 struct plat_stmmacenet_data *plat)
827 plat->bus_id = 2;
828 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
832 return tgl_common_data(pdev, plat);
902 struct plat_stmmacenet_data *plat)
907 common_default_data(plat);
925 plat->bus_id = pci_dev_id(pdev);
926 plat->phy_addr = ret;
927 plat->phy_interface = PHY_INTERFACE_MODE_RMII;
929 plat->dma_cfg->pbl = 16;
930 plat->dma_cfg->pblx8 = true;
931 plat->dma_cfg->fixed_burst = 1;
942 struct plat_stmmacenet_data *plat,
956 plat->flags &= ~STMMAC_FLAG_MULTI_MSI_EN;
964 struct plat_stmmacenet_data *plat,
970 if (plat->msi_rx_base_vec >= STMMAC_MSI_VEC_MAX ||
971 plat->msi_tx_base_vec >= STMMAC_MSI_VEC_MAX) {
986 for (i = 0; i < plat->rx_queues_to_use; i++) {
988 plat->msi_rx_base_vec + i * 2);
992 for (i = 0; i < plat->tx_queues_to_use; i++) {
994 plat->msi_tx_base_vec + i * 2);
997 if (plat->msi_mac_vec < STMMAC_MSI_VEC_MAX)
998 res->irq = pci_irq_vector(pdev, plat->msi_mac_vec);
999 if (plat->msi_wol_vec < STMMAC_MSI_VEC_MAX)
1000 res->wol_irq = pci_irq_vector(pdev, plat->msi_wol_vec);
1001 if (plat->msi_lpi_vec < STMMAC_MSI_VEC_MAX)
1002 res->lpi_irq = pci_irq_vector(pdev, plat->msi_lpi_vec);
1003 if (plat->msi_sfty_ce_vec < STMMAC_MSI_VEC_MAX)
1004 res->sfty_ce_irq = pci_irq_vector(pdev, plat->msi_sfty_ce_vec);
1005 if (plat->msi_sfty_ue_vec < STMMAC_MSI_VEC_MAX)
1006 res->sfty_ue_irq = pci_irq_vector(pdev, plat->msi_sfty_ue_vec);
1008 plat->flags |= STMMAC_FLAG_MULTI_MSI_EN;
1031 struct plat_stmmacenet_data *plat;
1039 plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL);
1040 if (!plat)
1043 plat->mdio_bus_data = devm_kzalloc(&pdev->dev,
1044 sizeof(*plat->mdio_bus_data),
1046 if (!plat->mdio_bus_data)
1049 plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg),
1051 if (!plat->dma_cfg)
1054 plat->safety_feat_cfg = devm_kzalloc(&pdev->dev,
1055 sizeof(*plat->safety_feat_cfg),
1057 if (!plat->safety_feat_cfg)
1074 plat->bsp_priv = intel_priv;
1082 plat->msi_mac_vec = STMMAC_MSI_VEC_MAX;
1083 plat->msi_wol_vec = STMMAC_MSI_VEC_MAX;
1084 plat->msi_lpi_vec = STMMAC_MSI_VEC_MAX;
1085 plat->msi_sfty_ce_vec = STMMAC_MSI_VEC_MAX;
1086 plat->msi_sfty_ue_vec = STMMAC_MSI_VEC_MAX;
1087 plat->msi_rx_base_vec = STMMAC_MSI_VEC_MAX;
1088 plat->msi_tx_base_vec = STMMAC_MSI_VEC_MAX;
1090 ret = info->setup(pdev, plat);
1097 if (plat->eee_usecs_rate > 0) {
1100 tx_lpi_usec = (plat->eee_usecs_rate / 1000000) - 1;
1104 ret = stmmac_config_multi_msi(pdev, plat, &res);
1106 ret = stmmac_config_single_msi(pdev, plat, &res);
1114 ret = stmmac_dvr_probe(&pdev->dev, plat, &res);
1122 clk_disable_unprepare(plat->stmmac_clk);
1123 clk_unregister_fixed_rate(plat->stmmac_clk);
1141 clk_disable_unprepare(priv->plat->stmmac_clk);
1142 clk_unregister_fixed_rate(priv->plat->stmmac_clk);